-
公开(公告)号：US10367053B2
公开(公告)日：2019-07-30
申请号：US15896491
申请日：2018-02-14
Applicant: Micron Technology, Inc.
Inventor： Yasuhiko Tanuma , Takashi Ishihara
Abstract: Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.
-
公开(公告)号：US20180175017A1
公开(公告)日：2018-06-21
申请号：US15896491
申请日：2018-02-14
Applicant: Micron Technology, Inc.
Inventor： Yasuhiko Tanuma , Takashi Ishihara
CPC classification number: H01L28/20 , G06F17/5072 , H01L27/0207 , H01L27/0288 , H01L27/0629 , H01L27/11807 , H01L28/00 , H01L29/7304
Abstract: Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.
-
公开(公告)号：US20220123550A1
公开(公告)日：2022-04-21
申请号：US17071562
申请日：2020-10-15
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Haruka Momota , Takashi Ishihara
Abstract: Disclosed herein is an apparatus that includes a first power ESD protection circuit arranged in a first circuit area; a plurality of data I/O circuits arranged in a second circuit area adjacent to the first circuit area in a first direction; a plurality of data I/O terminals arranged in the second circuit area, each of the plurality of data I/O terminals being coupled to an associated one of the plurality of data I/O circuits; a plurality of first power terminals arranged in the second circuit area; and a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.
-
公开(公告)号：US10916497B2
公开(公告)日：2021-02-09
申请号：US16144615
申请日：2018-09-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Takashi Ishihara , Wataru Nobehara
IPC: H01L23/522 , H01L27/02 , H01L27/105 , H01L23/00
Abstract: A semiconductor device may include a multi-level wiring structure comprising a first-level wiring layer, a second-level wiring layer and an insulating layer between the first-level wiring layer and the second-level wiring layer. The device may also include a bond pad, a first wiring extending from the bond pad, and a second wiring overlapping at least in part with the first wiring through the insulating layer to be capacitively coupled to the first wiring. The first wiring and the second wiring may each be formed respectively as the first-level wiring layer and the second-level wiring layer. The device may also include a protection circuit configured to be DC coupled to the second wiring. The first-level wiring layer may include a redistribution layer (RDL).
-
公开(公告)号：US20210035968A1
公开(公告)日：2021-02-04
申请号：US17076626
申请日：2020-10-21
Applicant: Micron Technology, Inc.
Inventor： Takashi Ishihara
IPC: H01L27/02 , H01L27/108 , G11C11/4093
Abstract: An apparatus including separate first and second active regions that are physically separate, with each region including one or more sets of doped regions that each define a current channel. The current channels on the first and second active regions are activated by a common gate signal.
-
Patent Agency Ranking
公开(公告)号：US20170256529A1
公开(公告)日：2017-09-07
申请号：US15063117
申请日：2016-03-07
Applicant: Micron Technology, Inc.
Inventor： Yasuhiko Tanuma , Takashi Ishihara
CPC classification number: H01L27/0207 , G06F17/5072 , H01L27/0629 , H01L27/11807
Abstract: Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.
-
公开(公告)号：US20240413195A1
公开(公告)日：2024-12-12
申请号：US18668134
申请日：2024-05-18
Applicant: Micron Technology, Inc.
Inventor： Takashi Ishihara
IPC: H01L29/06 , H01L21/762 , H01L23/522 , H01L29/417 , H10B10/00 , H10B12/00
Abstract: A semiconductor device including a substrate; a first active region disposed in the substrate, the first active region having one or more first type channels and a first plurality of doped regions; a second active region disposed in the substrate, the second active region having one or more second type channels and a second plurality of doped regions, the second active region being physically separated from the first active region by a STI region; an intermediate wiring layer disposed above the substrate, the intermediate wiring layer having a plurality of fingers connected to the first plurality of doped regions and the second plurality of doped regions, respectively; and a metal wiring layer having a source finger and a drain finger, wherein the source finger is connected to a first group of the plurality of fingers, and the drain finger is connected to a second group of the plurality of fingers.
-
公开(公告)号：US20200212029A1
公开(公告)日：2020-07-02
申请号：US16234358
申请日：2018-12-27
Applicant: Micron Technology, Inc.
Inventor： Takashi Ishihara
IPC: H01L27/02 , G11C11/4093 , H01L27/108
Abstract: An apparatus includes: a first substrate comprising a first channel that includes a first plurality of doped regions on the first substrate; a second substrate comprising a second channel that includes a second plurality of doped regions in the second substrate, wherein: the doped regions of the second substrate are electrically and/or physically separate from those of the first substrate, and the second channel is aligned colinearly with the first channel; and a conductive structure extending across the first substrate and the second substrate and electrically connecting matching doped regions of the first channel and the second channel.
-
公开(公告)号：US11764571B2
公开(公告)日：2023-09-19
申请号：US17071562
申请日：2020-10-15
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Haruka Momota , Takashi Ishihara
CPC classification number: H02H9/046 , H01L27/0248 , H01L27/0296
Abstract: Disclosed herein is an apparatus that includes a first power ESD protection circuit arranged in a first circuit area; a plurality of data I/O circuits arranged in a second circuit area adjacent to the first circuit area in a first direction; a plurality of data I/O terminals arranged in the second circuit area, each of the plurality of data I/O terminals being coupled to an associated one of the plurality of data I/O circuits; a plurality of first power terminals arranged in the second circuit area; and a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.
-
10.发明授权公开(公告)号：US11742306B2
公开(公告)日：2023-08-29
申请号：US17180552
申请日：2021-02-19
Applicant: Micron Technology, Inc.
Inventor： Takashi Ishihara
CPC classification number: H01L24/06 , G11C5/14 , H01L24/05 , H01L2224/04042 , H01L2224/05548 , H01L2224/05554
Abstract: Layouts for pads and conductive lines of memory devices are disclosed. A memory device may include memory cells and conductive lines arranged above memory cells. The conductive lines may extend from substantially a first side of the memory device to substantially a second side of the memory device. Each of the conductive lines may be electrically coupled to a bond pad, a first probe pad and a second probe pad. The bond pad may be positioned at or near the first side and be configured to receive power. The first probe pad may be positioned at or near the first side and be configured to be electrically coupled to a probe. The second probe pad may be positioned at or near the second side. Associated systems and methods are also disclosed.
-
-
-
-
-
-
-
-
-
Search Results
14
records
(took 0.014 seconds)
