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公开(公告)号：US20230377967A1
公开(公告)日：2023-11-23
申请号：US17751297
申请日：2022-05-23
发明人： Keizo Kawakita , Hidenori Yamaguchi
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L21/76816 , H01L21/31144
摘要： Disclosed herein is a method that includes: forming a mask layer on a semiconductor substrate; forming a photoresist on the mask layer; performing non-uniform exposure on the photoresist to provide a first patterned photoresist which includes a first region where the photoresist is removed to expose the mask layer and a second region where a part of the photoresist remains; first etching using the first patterned photoresist to remove the mask layer in the first region and form a first trench in the first region of the semiconductor substrate; second etching to provide a second patterned photoresist which includes the second region where the photoresist is removed; third etching using the second patterned photoresist to remove the mask layer in the second region; and fourth etching to deepen the first trench in the first region and form a second trench shallower than the first trench in the second region.
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公开(公告)号：US20230187289A1
公开(公告)日：2023-06-15
申请号：US17550741
申请日：2021-12-14
发明人： Haruka Momota , Koji Yasumori , Keizo Kawakita
IPC分类号： H01L21/66 , H01L21/768 , H01L23/528 , H01L23/525
CPC分类号： H01L22/32 , H01L21/76802 , H01L23/528 , H01L23/5256 , H01L27/10897
摘要： An apparatus includes an active region; a scribe region surrounding the active region; a test component in the scribe region; a pad electrode in the active region; and a power supply wiring of an upper wiring layer in the active region, the power supply wiring extending between the test component and the pad electrode; and an interconnection structure coupling the test component and the pad electrode across a border between the active region and the scribe region, the interconnection structure including a wiring portion of a lower wiring layer crossing the power supply wiring.
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公开(公告)号：US20220336372A1
公开(公告)日：2022-10-20
申请号：US17230772
申请日：2021-04-14
IPC分类号： H01L23/00 , H01L23/544
摘要： Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner including polymer; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.
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公开(公告)号：US20220059346A1
公开(公告)日：2022-02-24
申请号：US17001301
申请日：2020-08-24
IPC分类号： H01L21/027 , H01L21/311 , H01L27/108
摘要： A method including forming an insulating film over first, second, third and fourth regions of a semiconductor substrate; forming a polyimide film on the insulating film; and patterning the polyimide film with a lithography method using a photomask including at least a first region of a first transmittance rate, a second region of a second transmittance rate, a third region. having a shading material, and a fourth region, wherein the first, second, third and fourth regions of the photomask correspond to the first, second, third and fourth regions of the semiconductor substrate, respectively.
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公开(公告)号：US12125789B2
公开(公告)日：2024-10-22
申请号：US17935282
申请日：2022-09-26
IPC分类号： H01L23/532 , H01L23/498 , H01L23/538 , H01L29/06
CPC分类号： H01L23/5329 , H01L23/49883 , H01L23/5383 , H01L29/0649
摘要： According to one or more embodiments, a method of manufacturing a semiconductor device including a plurality of main circuit regions arranged in a matrix and a scribe region provided between the main circuit regions is provided. The method includes: forming a first insulating film; forming a low-k film; forming a plurality of penetrating portions penetrating through the low-k film; and forming a second insulating film under low-coverage film-forming conditions to form cavities in the plurality of through-holes.
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公开(公告)号：US11769736B2
公开(公告)日：2023-09-26
申请号：US17230772
申请日：2021-04-14
IPC分类号： H01L23/00 , H01L23/544 , H10B12/00
CPC分类号： H01L23/562 , H01L23/544 , H01L2223/5446 , H10B12/00
摘要： Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner including polymer; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.
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公开(公告)号：US11658121B2
公开(公告)日：2023-05-23
申请号：US16885026
申请日：2020-05-27
IPC分类号： H01L23/532 , H01L23/528 , H10B12/00
CPC分类号： H01L23/53295 , H01L23/5283 , H10B12/0335 , H10B12/31
摘要： A semiconductor device includes a semiconductor substrate; a first insulating film and a second insulating film provided above the semiconductor substrate; a low-k film provided between the first insulating film and the second insulating film; an element formation region in which elements included in an electric circuit are formed in the semiconductor substrate; a scribe region provided around the element formation region; a cut portion provided on the outer periphery of the scribe region; and a groove formed between the cut portion and the element formation region, wherein the groove penetrates through the low-k film.
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公开(公告)号：US11587870B2
公开(公告)日：2023-02-21
申请号：US16539437
申请日：2019-08-13
IPC分类号： H01L23/528 , H01L23/532 , H01L27/108
摘要： An apparatus comprising a multilevel wiring structure comprising aluminum interconnections. The aluminum interconnections comprise a first portion, a second portion, and a third portion, where the second portion is between the first portion and the third portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. A memory device comprising a memory array comprising memory cells and a control logic component electrically connected to the memory array. At least one of the memory cells comprises a multilevel wiring structure comprising interconnect structures, where the interconnect structures comprise a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. Related apparatus, memory devices, and methods are also disclosed.
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公开(公告)号：US20230011222A1
公开(公告)日：2023-01-12
申请号：US17935282
申请日：2022-09-26
IPC分类号： H01L23/532 , H01L29/06 , H01L23/498 , H01L23/538
摘要： According to one or more embodiments, a method of manufacturing a semiconductor device including a plurality of main circuit regions arranged in a matrix and a scribe region provided between the main circuit regions is provided. The method includes: forming a first insulating film; forming a low-k film; forming a plurality of penetrating portions penetrating through the low-k film; and forming a second insulating film under low-coverage film-forming conditions to form cavities in the plurality of through-holes.
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公开(公告)号：US20200211982A1
公开(公告)日：2020-07-02
申请号：US16236143
申请日：2018-12-28
发明人： Shams U. Arifeen , Hyunsuk Chun , Sheng Wei Yang , Keizo Kawakita
IPC分类号： H01L23/00
摘要： Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.
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