公开(公告)号：US20230238051A1

公开(公告)日：2023-07-27

申请号：US17649173

申请日：2022-01-27

申请人： MICRON TECHNOLOGY, INC.

发明人： John Schreck

IPC分类号： G11C11/4091 ,  G11C11/4074 ,  G11C11/4093 ,  G11C5/06

CPC分类号： G11C11/4091 ,  G11C11/4074 ,  G11C11/4093 ,  G11C5/06

摘要： Local input/output (LIO) lines may be used for precharging and equalizing the digit lines associated with a sense amplifier. The precharge device and equalization device of the associated sense amplifier may be omitted in some examples. In some examples, an equalization device may short the lines of a LIO line pair together. The LIO line pair may drive one or more pairs of digit lines to a precharge potential. Digit lines may be connected to the LIO line pair and driven to a midpoint potential in some examples.

公开(公告)号：US11600326B2

公开(公告)日：2023-03-07

申请号：US17154945

申请日：2021-01-21

申请人： MICRON TECHNOLOGY, INC.

发明人： John Schreck ,  Dan Penney

IPC分类号： G11C15/04 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/419 ,  G11C16/28

摘要： Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

公开(公告)号：US08902688B2

公开(公告)日：2014-12-02

申请号：US14054205

申请日：2013-10-15

申请人： Micron Technology, Inc.

发明人： John Schreck ,  John R. Wilford

IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C11/402

CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4061

摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

摘要翻译： 用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。 当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。 在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。 隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且在控制信号被断言时以第一刷新率刷新动态数据。 所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

公开(公告)号：US20140043919A1

公开(公告)日：2014-02-13

申请号：US14054205

申请日：2013-10-15

申请人： Micron Technology, Inc.

发明人： John Schreck ,  John R. Wilford

IPC分类号： G11C11/402

CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4061

摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

摘要翻译： 用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。 当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。 在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。 隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且在控制信号被断言时以第一刷新率刷新动态数据。 所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

公开(公告)号：US20230223069A1

公开(公告)日：2023-07-13

申请号：US17573854

申请日：2022-01-12

申请人： MICRON TECHNOLOGY, INC.

发明人： John Schreck

IPC分类号： G11C11/408

CPC分类号： G11C11/4085 ,  G11C11/4087

摘要： In some examples, a main word line driver may include a transistor that is driven between an on state and a high resistance state by a signal based, at least in part, on a row address. In both states, the transistor may maintain a main word line in an inactive state. When in the high resistance state, the transistor may be overridden by a decoder that drives the main word line to an active state. In some examples, a main word line driver may include a transistor maintained in a high resistance state coupled in parallel with another transistor that may be driven between an on state and an off state by a signal based, at least in part, on a row address. When the other transistor is in the off state, the high resistance state transistor may be overridden by a decoder that drives a main word line to an active state.

公开(公告)号：US11264096B2

公开(公告)日：2022-03-01

申请号：US16411573

申请日：2019-05-14

申请人： MICRON TECHNOLOGY, INC.

发明人： John Schreck ,  Dan Penney

IPC分类号： G11C15/04 ,  G11C16/28 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/419 ,  G11C11/4094

摘要： Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

公开(公告)号：US20210142852A1

公开(公告)日：2021-05-13

申请号：US17154945

申请日：2021-01-21

申请人： MICRON TECHNOLOGY, INC.

发明人： John Schreck ,  Dan Penney

IPC分类号： G11C15/04 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/419 ,  G11C16/28

摘要： Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

公开(公告)号：US12002504B2

公开(公告)日：2024-06-04

申请号：US17563229

申请日：2021-12-28

申请人： MICRON TECHNOLOGY, INC.

发明人： John Schreck

IPC分类号： G11C11/4091 ,  G11C11/408

CPC分类号： G11C11/4091 ,  G11C11/4085

摘要： Components of sense amplifiers may share contacts that couple the components to a global line via a local line. In some examples, the components may be pull-down circuits of a same sense amplifier or pull-down circuits of adjacent sense amplifiers. The shared contact may include a transistor or a resistance between the local line and the global line. In some examples, the global line may be an RNL line. The transistor or resistance may reduce the impact of voltage across the components from affecting the global line and/or reduce the impact of voltage changes on the global line on the individual components.

公开(公告)号：US20230206990A1

公开(公告)日：2023-06-29

申请号：US17563229

申请日：2021-12-28

申请人： MICRON TECHNOLOGY, INC.

发明人： John Schreck

IPC分类号： G11C11/4091 ,  G11C11/408

CPC分类号： G11C11/4091 ,  G11C11/4085

摘要： Components of sense amplifiers may share contacts that couple the components to a global line via a local line. In some examples, the components may be pull-down circuits of a same sense amplifier or pull-down circuits of adjacent sense amplifiers. The shared contact may include a transistor or a resistance between the local line and the global line. In some examples, the global line may be an RNL line. The transistor or resistance may reduce the impact of voltage across the components from affecting the global line and/or reduce the impact of voltage changes on the global line on the individual components.

公开(公告)号：US10930349B2

公开(公告)日：2021-02-23

申请号：US16411573

申请日：2019-05-14

申请人： MICRON TECHNOLOGY, INC.

发明人： John Schreck ,  Dan Penney

IPC分类号： G11C15/04 ,  G11C16/28 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/419

摘要： Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.