公开(公告)号：US20210097209A1

公开(公告)日：2021-04-01

申请号：US16589989

申请日：2019-10-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chikara Kondo ,  Kazuhiro Kurihara

IPC: G06F21/85 ,  G06F21/79 ,  G06F21/60 ,  G06F12/14 ,  G11C29/12

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for signal encryption in high bandwidth memory. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.

公开(公告)号：US10803923B2

公开(公告)日：2020-10-13

申请号：US16444365

申请日：2019-06-18

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa ,  Kazuhiro Kurihara ,  Kohei Nakamura ,  Akira Yamashita

IPC: G11C11/4076 ,  H03K5/1534 ,  H03K5/05 ,  H03K3/037 ,  H03K5/135 ,  G11C7/22 ,  H03K5/15 ,  H03K5/00

Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.

公开(公告)号：US11720719B2

公开(公告)日：2023-08-08

申请号：US16589989

申请日：2019-10-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chikara Kondo ,  Kazuhiro Kurihara

IPC: G06F21/85 ,  G06F21/79 ,  G11C29/12 ,  G06F12/14 ,  G06F21/60

CPC classification number: G06F21/85 ,  G06F12/1408 ,  G06F21/602 ,  G06F21/79 ,  G11C29/1201

Abstract: Apparatuses, systems, and methods for signal encryption in high bandwidth memory are described. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.

公开(公告)号：US20230351063A1

公开(公告)日：2023-11-02

申请号：US18333406

申请日：2023-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chikara Kondo ,  Kazuhiro Kurihara

IPC: G06F21/85 ,  G06F21/79 ,  G11C29/12 ,  G06F12/14 ,  G06F21/60

CPC classification number: G06F21/85 ,  G06F21/79 ,  G11C29/1201 ,  G06F12/1408 ,  G06F21/602

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for signal encryption in high bandwidth memory. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.

公开(公告)号：US10339998B1

公开(公告)日：2019-07-02

申请号：US15937552

申请日：2018-03-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Kazuhiro Kurihara ,  Kohei Nakamura ,  Akira Yamashita

IPC: G11C11/4076 ,  H03K5/1534 ,  H03K5/05 ,  H03K3/037 ,  H03K5/135 ,  H03K5/00

Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.

公开(公告)号：US20190304532A1

公开(公告)日：2019-10-03

申请号：US16444365

申请日：2019-06-18

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa ,  Kazuhiro Kurihara ,  Kohei Nakamura ,  Akira Yamashita

IPC: G11C11/4076 ,  H03K5/135 ,  H03K3/037 ,  H03K5/1534 ,  H03K5/05

Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.