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公开(公告)号:US11335393B2
公开(公告)日:2022-05-17
申请号:US17173048
申请日:2021-02-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Yoshiro Riho , Yoshinori Matsui , Kiyohiro Furutani , Takahiko Fukiage , Ki-Jun Nam , John D. Porter
IPC: G11C11/406 , G11C11/4076 , G11C11/408
Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.
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公开(公告)号:US10923171B2
公开(公告)日:2021-02-16
申请号:US16163422
申请日:2018-10-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Yoshiro Riho , Yoshinori Matsui , Kiyohiro Furutani , Takahiko Fukiage , Ki-Jun Nam , John D. Porter
IPC: G11C11/406 , G11C11/4076 , G11C11/408
Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.
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公开(公告)号:US11274977B2
公开(公告)日:2022-03-15
申请号:US16228377
申请日:2018-12-20
Applicant: Micron Technology, Inc.
Inventor: Kiyohiro Furutani
Abstract: Disclosed here is an apparatus that includes a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes.
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公开(公告)号:US20210166753A1
公开(公告)日:2021-06-03
申请号:US17173048
申请日:2021-02-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Yoshiro Riho , Yoshinori Matsui , Kiyohiro Furutani , Takahiko Fukiage , Ki-Jun Nam , John D. Porter
IPC: G11C11/406 , G11C11/4076 , G11C11/408
Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times When the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.
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公开(公告)号:US10168233B2
公开(公告)日:2019-01-01
申请号:US14707951
申请日:2015-05-08
Applicant: Micron Technology, Inc.
Inventor: Kiyohiro Furutani
Abstract: Disclosed here is an apparatus that includes a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes.
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公开(公告)号:US09618562B2
公开(公告)日:2017-04-11
申请号:US14472226
申请日:2014-08-28
Applicant: Micron Technology, Inc.
Inventor: Kiyohiro Furutani
CPC classification number: G01R31/2644 , G11C5/147 , G11C29/006 , G11C29/12005
Abstract: Disclosed herein is an apparatus that includes a first internal-potential generation circuit that generates a first internal potential from a power supply potential and that outputs the first internal potential to a first node, and an internal-potential force circuit that includes a first switch element provided between the first node and a second external terminal. The internal-potential force circuit causes the first switch element to enter into an off-state when the test signal supplied to a third external terminal is activated and a potential level of a first external terminal is a first level, and causes the first switch element to enter into an on-state when the test signal supplied to the third external terminal is activated and the potential level of the first external terminal is a second level different from the first level.
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公开(公告)号:US20150061722A1
公开(公告)日:2015-03-05
申请号:US14472226
申请日:2014-08-28
Applicant: Micron Technology, Inc.
Inventor: Kiyohiro Furutani
IPC: G01R31/26
CPC classification number: G01R31/2644 , G11C5/147 , G11C29/006 , G11C29/12005
Abstract: Disclosed herein is an apparatus that includes a first internal-potential generation circuit that generates a first internal potential from a power supply potential and that outputs the first internal potential to a first node, and an internal-potential force circuit that includes a first switch element provided between the first node and a second external terminal. The internal-potential force circuit causes the first switch element to enter into an off-state when the test signal supplied to a third external terminal is activated and a potential level of a first external terminal is a first level, and causes the first switch element to enter into an on-state when the test signal supplied to the third external terminal is activated and the potential level of the first external terminal is a second level different from the first level.
Abstract translation: 本文公开了一种装置,其包括:第一内部电位产生电路,其从电源电位产生第一内部电位,并将第一内部电位输出到第一节点;以及内部电位力电路,其包括第一开关元件 设置在第一节点和第二外部终端之间。 当提供给第三外部端子的测试信号被激活并且第一外部端子的电位电平为第一电平时,内部势力电路使得第一开关元件进入截止状态,并且使第一开关元件 当提供给第三外部端子的测试信号被激活并且第一外部端子的电位电平是与第一电平不同的第二电平时,进入导通状态。
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公开(公告)号:US20190120704A1
公开(公告)日:2019-04-25
申请号:US16228377
申请日:2018-12-20
Applicant: Micron Technology, Inc.
Inventor: Kiyohiro Furutani
Abstract: Disclosed here is an apparatus that includes a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes.
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