公开(公告)号：US11335393B2

公开(公告)日：2022-05-17

申请号：US17173048

申请日：2021-02-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Yoshinori Matsui ,  Kiyohiro Furutani ,  Takahiko Fukiage ,  Ki-Jun Nam ,  John D. Porter

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

公开(公告)号：US10923171B2

公开(公告)日：2021-02-16

申请号：US16163422

申请日：2018-10-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Yoshinori Matsui ,  Kiyohiro Furutani ,  Takahiko Fukiage ,  Ki-Jun Nam ,  John D. Porter

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

公开(公告)号：US09679614B1

公开(公告)日：2017-06-13

申请号：US14952489

申请日：2015-11-25

Applicant: Micron Technology, Inc.

Inventor： Yoshinori Matsui

IPC: G11C5/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G11C5/06 ,  G11C11/4096 ,  G11C7/10

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1048 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097

Abstract: Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.

公开(公告)号：US20230170013A1

公开(公告)日：2023-06-01

申请号：US17700289

申请日：2022-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Shun Nishimura ,  Yoshinori Matsui

IPC: G11C11/4096 ,  G11C11/4093 ,  H03K19/003

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  H03K19/00384

Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

公开(公告)号：US20210166753A1

公开(公告)日：2021-06-03

申请号：US17173048

申请日：2021-02-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Yoshinori Matsui ,  Kiyohiro Furutani ,  Takahiko Fukiage ,  Ki-Jun Nam ,  John D. Porter

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times When the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

公开(公告)号：US20170236560A1

公开(公告)日：2017-08-17

申请号：US15493816

申请日：2017-04-21

Applicant: Micron Technology, Inc.

Inventor： Yoshinori Matsui

IPC: G11C5/06 ,  G11C11/4094 ,  G11C11/4091

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1048 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097

Abstract: Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.

公开(公告)号：US09875786B2

公开(公告)日：2018-01-23

申请号：US15333507

申请日：2016-10-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tetsuya Arai ,  Yoshinori Matsui

IPC: G11C7/10 ,  G11C11/4093 ,  H03K17/687 ,  G11C11/4096 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/50 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C7/1057 ,  G11C7/106 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  H03K17/687

Abstract: A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in a push-pull manner. Each of the first and second output circuits includes a plurality of output transistors. The cutting circuit is rendered non-conductive when each of the transistors in the first and second output circuits is rendered non-conductive.

公开(公告)号：US09263104B2

公开(公告)日：2016-02-16

申请号：US14184566

申请日：2014-02-19

Applicant: Micron Technology, Inc.

Inventor： Yoshinori Matsui

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4097

CPC classification number: G11C7/1078 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/107

Abstract: Disclosed herein is an apparatus that includes: a first terminal configured to receive a serial write data signal that includes at least four bits transferred in series with each other; a second terminal configured to receive a data strobe signal; a control circuit configured to produce a plurality of internal data strobe signals in response to the data strobe signal; and a serial-to-parallel conversion circuit configured to respond to the data strobe and internal data strobe signals to convert the serial write data signal into a parallel write data signal that includes at least four bits produced in parallel to each other.

Abstract translation: 本文公开了一种装置，其包括：第一终端，被配置为接收串行写入数据信号，所述串行写入数据信号包括彼此串联传送的至少四个位; 配置为接收数据选通信号的第二终端; 控制电路，被配置为响应于所述数据选通信号产生多个内部数据选通信号; 以及串行到并行转换电路，被配置为响应于数据选通信号和内部数据选通信号，以将串行写入数据信号转换成包括至少四个彼此并行产生的位的并行写入数据信号。

公开(公告)号：US20140241073A1

公开(公告)日：2014-08-28

申请号：US14184566

申请日：2014-02-19

Applicant: Micron Technology, Inc.

Inventor： Yoshinori Matsui

IPC: G11C7/22

CPC classification number: G11C7/1078 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/107

Abstract: Disclosed herein is an apparatus that includes: a first terminal configured to receive a serial write data signal that includes at least four bits transferred in series with each other; a second terminal configured to receive a data strobe signal; a control circuit configured to produce a plurality of internal data strobe signals in response to the data strobe signal; and a serial-to-parallel conversion circuit configured to respond to the data strobe and internal data strobe signals to convert the serial write data signal into a parallel write data signal that includes at least four bits produced in parallel to each other.

Abstract translation: 本文公开了一种装置，其包括：第一终端，被配置为接收串行写入数据信号，所述串行写入数据信号包括彼此串联传送的至少四个位; 配置为接收数据选通信号的第二终端; 控制电路，被配置为响应于所述数据选通信号产生多个内部数据选通信号; 以及串行到并行转换电路，被配置为响应于数据选通信号和内部数据选通信号，以将串行写入数据信号转换成包括至少四个彼此并行产生的位的并行写入数据信号。

公开(公告)号：US12237001B2

公开(公告)日：2025-02-25

申请号：US17700289

申请日：2022-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Shun Nishimura ,  Yoshinori Matsui

IPC: G11C11/4096 ,  G11C11/4093 ,  H03K19/003

Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.