公开(公告)号：US20180130739A1

公开(公告)日：2018-05-10

申请号：US15344211

申请日：2016-11-04

Applicant: Micron Technology, Inc.

Inventor： Yuki Miura ,  Mieko Kojima

IPC: H01L23/522 ,  G11C5/06 ,  G11C7/22

CPC classification number: H01L23/5226 ,  G11C5/06 ,  G11C5/063 ,  G11C7/22 ,  G11C29/022 ,  G11C29/028

Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality of pads disposed at an edge of the apparatus; a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks including a via disposed at a side opposite to the pad formation area with respect to each circuit block; and a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via.

公开(公告)号：US10347577B2

公开(公告)日：2019-07-09

申请号：US15973046

申请日：2018-05-07

Applicant: Micron Technology, Inc.

Inventor： Yuki Miura ,  Mieko Kojima

IPC: G11C5/06 ,  H01L23/522 ,  G11C7/22 ,  G11C29/02

Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality of pads disposed at an edge of the apparatus; a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks including a via disposed at a side opposite to the pad formation area with respect to each circuit block; and a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via.

公开(公告)号：US10156893B1

公开(公告)日：2018-12-18

申请号：US15628543

申请日：2017-06-20

Applicant: Micron Technology, Inc.

Inventor： Mieko Kojima

IPC: H03K19/003 ,  G06F3/00 ,  H03K19/096 ,  H04L25/03 ,  H03K19/0175 ,  H04L25/02

Abstract: Apparatuses in data input/output circuits of a semiconductor device are described. An example apparatus includes an output driver and a pre-output driver. The pre-output driver includes: an output terminal coupled to the output driver and provides an output signal to the output driver; an output stage that receives a data signal and provides the output signal to the output terminal responsive, at least in part, to the data signal; and a slew rate control stage coupled to the output stage and controls a current flowing through the output stage. The output stage is disposed between the slew rate control stage and the output terminal.

公开(公告)号：US20240312498A1

公开(公告)日：2024-09-19

申请号：US18674788

申请日：2024-05-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mieko Kojima ,  Kazuyuki Morishige ,  Tetsuya Arai ,  Guangcan Chen

IPC: G11C7/10 ,  G11C5/06 ,  H03K19/017

CPC classification number: G11C7/1057 ,  G11C5/06 ,  G11C7/1039 ,  H03K19/01721

Abstract: Some embodiments provide an apparatus including a semiconductor substrate having source regions and regions alternately arranged in a first direction; gate electrodes between the source regions and the drain regions; a first wiring layer including first conductive patterns covering the source regions and second conductive patterns covering the drain regions; first via conductors between the first conductive patterns and the source regions; second via conductors between the second conductive patterns and the drain regions; a second wiring layer over the first wiring layer, including third conductive patterns covering the first conductive patterns and fourth conductive patterns covering the second conductive patterns; third via conductors between the third conductive patterns and the first conductive patterns; and fourth via conductors between the fourth conductive patterns and the second conductive patterns. The fourth via conductors are shifted from the third via conductors in a second direction perpendicular to the first direction.

公开(公告)号：US12020768B2

公开(公告)日：2024-06-25

申请号：US17563852

申请日：2021-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mieko Kojima ,  Kazuyuki Morishige ,  Tetsuya Arai ,  Guangcan Chen

IPC: G11C7/10 ,  G11C5/06 ,  H03K19/017

CPC classification number: G11C7/1057 ,  G11C5/06 ,  G11C7/1039 ,  H03K19/01721

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.

公开(公告)号：US11466685B2

公开(公告)日：2022-10-11

申请号：US17138252

申请日：2020-12-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mieko Kojima

IPC: G11C7/10 ,  F04C18/02 ,  H01L27/108 ,  G11C11/409 ,  G11C7/22 ,  F04C29/00 ,  F01C17/06

Abstract: Disclosed herein is an apparatus that includes a first buffer circuit, a plurality of first driver circuits configured to drive the first buffer circuit, and a plurality of first switch circuits configured to supply an operation voltage to the first driver circuits, respectively. The first driver circuits are collectively arranged in a first region in a matrix, and the first switch circuits are collectively arranged in a second region different from the first region.

公开(公告)号：US10885955B2

公开(公告)日：2021-01-05

申请号：US16374613

申请日：2019-04-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mieko Kojima

IPC: G11C7/10 ,  H01L27/108 ,  G11C11/409 ,  G11C7/22

Abstract: Disclosed herein is an apparatus that includes a rust buffer circuit, a plurality of first driver circuits configured to drive the first buffer circuit, and a plurality of first switch circuits configured to supply an operation voltage to the first driver circuits, respectively. The first driver circuits are collectively arranged in a first region in a matrix, and the first switch circuits are collectively arranged in a second region different from the first region.

公开(公告)号：US20180254245A1

公开(公告)日：2018-09-06

申请号：US15973046

申请日：2018-05-07

Applicant: Micron Technology, Inc.

Inventor： Yuki Miura ,  Mieko Kojima

IPC: H01L23/522 ,  G11C7/22 ,  G11C5/06

CPC classification number: H01L23/5226 ,  G11C5/06 ,  G11C5/063 ,  G11C7/22 ,  G11C29/022 ,  G11C29/028 ,  H01L24/00

Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality of pads disposed at an edge of the apparatus; a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks including a via disposed at a side opposite to the pad formation area with respect to each circuit block; and a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via.

公开(公告)号：US20230206966A1

公开(公告)日：2023-06-29

申请号：US17563852

申请日：2021-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mieko Kojima ,  Kazuyuki Morishige ,  Tetsuya Arai ,  Guangcan Chen

IPC: G11C7/10 ,  G11C5/06 ,  H03K19/017

CPC classification number: G11C7/1057 ,  G11C5/06 ,  G11C7/1039 ,  H03K19/01721

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.

公开(公告)号：US20210118476A1

公开(公告)日：2021-04-22

申请号：US17138252

申请日：2020-12-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mieko Kojima

IPC: G11C7/10 ,  H01L27/108 ,  G11C11/409 ,  G11C7/22

Abstract: Disclosed herein is an apparatus that includes a first buffer circuit, a plurality of first driver circuits configured to drive the first buffer circuit, and a plurality of first switch circuits configured to supply an operation voltage to the first driver circuits, respectively. The first driver circuits are collectively arranged in a first region in a matrix, and the first switch circuits are collectively arranged in a second region different from the first region.