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    APPARATUSES AND METHODS FOR SIGNAL TRANSMISSION PRECONDITIONING
    1.
    发明公开
    APPARATUSES AND METHODS FOR SIGNAL TRANSMISSION PRECONDITIONING 审中-公开

    公开(公告)号：US20230377631A1

    公开(公告)日：2023-11-23

    申请号：US17749563

    申请日：2022-05-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Atsushi Mamba ,  Tetsuya Arai ,  Guangcan Chen

    IPC: G11C11/4093 ,  G11C11/4076

    CPC classification number: G11C11/4093 ,  G11C11/4076

    Abstract: Embodiments of the disclosure include signal processing methods to precondition signals for transmission on a high speed bus. A preconditioning circuit is configured to receive a serialized data signal at an input node and to precondition the serialized output data signal to provide a preconditioned output signal at an output node. The preconditioning circuit may include a feedback circuit coupled between the input node and the output node that is configured to independently control both of a propagation delay between the output node and the input node and a magnitude of emphasis/de-emphasis applied to a signal at the output node for provision to the input node.

    SEMICONDUCTOR DEVICE HAVING OUTPUT BUFFER
    2.
    发明公开
    SEMICONDUCTOR DEVICE HAVING OUTPUT BUFFER 审中-公开

    公开(公告)号：US20230206966A1

    公开(公告)日：2023-06-29

    申请号：US17563852

    申请日：2021-12-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Mieko Kojima ,  Kazuyuki Morishige ,  Tetsuya Arai ,  Guangcan Chen

    IPC: G11C7/10 ,  G11C5/06 ,  H03K19/017

    CPC classification number: G11C7/1057 ,  G11C5/06 ,  G11C7/1039 ,  H03K19/01721

    Abstract: Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.

    Semiconductor memory device having an output buffer controller
    3.
    发明授权
    Semiconductor memory device having an output buffer controller 有权
    具有输出缓冲器控制器的半导体存储器件

    公开(公告)号：US09324410B2

    公开(公告)日：2016-04-26

    申请号：US14476186

    申请日：2014-09-03

    Applicant: Micron Technology, Inc.

    Inventor： Tetsuya Arai

    IPC: G11C7/10 ,  G11C11/4093

    CPC classification number: G11C11/4093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C2207/2254

    Abstract: A device includes a data output terminal, an output buffer including n first transistors (n is a natural number greater than 1) connected in parallel with the data output terminal, and a calibration circuit to output an n-bit first code signal for controlling each of the n first transistors. In some embodiments, the calibration circuit includes a first counter circuit to output a k-bit second code signal (k is a natural number less than n), and a first code conversion circuit to convert the k-bit second code signal to the n-bit first code signal. Additional apparatus, systems, and methods are disclosed.

    Abstract translation: 一种装置包括数据输出端子，包括与数据输出端并联连接的n个第一晶体管（n为大于1的自然数）的输出缓冲器和用于输出用于控制每个的n位第一代码信号的校准电路 的n个第一晶体管。 在一些实施例中，校准电路包括用于输出k位第二代码信号（k是小于n的自然数）的第一计数器电路和将k位第二代码信号转换为n的第一代码转换电路 位第一码信号。 公开了附加装置，系统和方法。

    Output buffer circuit with non-target ODT function
    4.
    发明授权
    Output buffer circuit with non-target ODT function 有权

    公开(公告)号：US10777257B1

    公开(公告)日：2020-09-15

    申请号：US16707783

    申请日：2019-12-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tetsuya Arai ,  Junki Taniguchi

    IPC: G11C11/40 ,  H03K19/177 ,  G11C11/4093 ,  G11C11/4096 ,  H03K19/00 ,  H03K3/037 ,  H03K19/094 ,  H03K19/17772 ,  H03H11/28 ,  H03K19/17784

    Abstract: Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.

    Semiconductor memory device including output buffer
    5.
    发明授权
    Semiconductor memory device including output buffer 有权

    公开(公告)号：US10269395B2

    公开(公告)日：2019-04-23

    申请号：US14705762

    申请日：2015-05-06

    Applicant: Micron Technology, Inc.

    Inventor： Tetsuya Arai ,  Junki Taniguchi

    IPC: G01R31/319 ,  G11C7/10 ,  G06F1/26

    Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

    Apparatuses and methods for signal transmission preconditioning
    8.
    发明授权
    Apparatuses and methods for signal transmission preconditioning 有权

    公开(公告)号：US11955166B2

    公开(公告)日：2024-04-09

    申请号：US17749563

    申请日：2022-05-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Atsushi Mamba ,  Tetsuya Arai ,  Guangcan Chen

    IPC: G11C7/00 ,  G11C11/4076 ,  G11C11/4093

    CPC classification number: G11C11/4093 ,  G11C11/4076

    Abstract: Embodiments of the disclosure include signal processing methods to precondition signals for transmission on a high speed bus. A preconditioning circuit is configured to receive a serialized data signal at an input node and to precondition the serialized output data signal to provide a preconditioned output signal at an output node. The pre-conditioning circuit may include a feedback circuit coupled between the input node and the output node that is configured to independently control both of a propagation delay between the output node and the input node and a magnitude of emphasis/de-emphasis applied to a signal at the output node for provision to the input node.

    APPARATUSES INCLUDING OUTPUT DRIVERS AND METHODS FOR PROVIDING OUTPUT DATA SIGNALS
    9.
    发明公开
    APPARATUSES INCLUDING OUTPUT DRIVERS AND METHODS FOR PROVIDING OUTPUT DATA SIGNALS 审中-公开

    公开(公告)号：US20230170013A1

    公开(公告)日：2023-06-01

    申请号：US17700289

    申请日：2022-03-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Shun Nishimura ,  Yoshinori Matsui

    IPC: G11C11/4096 ,  G11C11/4093 ,  H03K19/003

    CPC classification number: G11C11/4096 ,  G11C11/4093 ,  H03K19/00384

    Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

    APPARATUSES AND METHODS FOR PRE-EMPHASIS CONTROL
    10.
    发明申请
    APPARATUSES AND METHODS FOR PRE-EMPHASIS CONTROL 有权

    公开(公告)号：US20220231891A1

    公开(公告)日：2022-07-21

    申请号：US17152660

    申请日：2021-01-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tetsuya Arai ,  Chihoko Yokobe ,  Guangcan Chen

    IPC: H04L25/03 ,  H03K19/017

    Abstract: Apparatuses and methods for pre-emphasis control are described. An example apparatus includes a pull-up circuit and a pull-down circuit. The pull-up circuit is configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal. The pull-down circuit is configured to receive a pull-down activation signal and drive a data terminal to a pull-down voltage responsive to an active pull-down data activation signal. The example apparatus further includes a pre-emphasis circuit that includes a pre-emphasis timing control circuit configured to provide a timing control signal, and further includes a logic circuit. A pre-emphasis control signal based on at least one of the pull-up and pull-down data activation signals is provided to control providing pre-emphasis having a timing based on a mode of operation.

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