公开(公告)号：US12260088B2

公开(公告)日：2025-03-25

申请号：US17663722

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Marco Onorato ,  Luca Porzio ,  Roberto Izzi ,  Nadav Grosz

IPC: G06F3/06

Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

公开(公告)号：US20240345925A1

公开(公告)日：2024-10-17

申请号：US18638245

申请日：2024-04-17

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Ferdinando Pascale ,  Roberto Izzi ,  Marco Onorato ,  Erminio Di Martino

IPC: G06F11/14 ,  G06F1/24 ,  G06F9/4401

CPC classification number: G06F11/1417 ,  G06F1/24 ,  G06F9/4405

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

公开(公告)号：US20240281169A1

公开(公告)日：2024-08-22

申请号：US18441869

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Rakeshkumar Dayabhai Vaghasiya ,  Roberto Izzi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0605 ,  G06F3/0632 ,  G06F3/0679

Abstract: Methods, systems, and devices for reliable and efficient boot logical unit access are described. For instance, a memory device may receive a request to write data to a boot logical unit of the memory device. The memory device may update a parameter from a first value to a second value based on receiving the request, the second value indicating a first stage of a procedure for updating the boot logical unit. The memory device may write, to a block of memory in the memory device, the data based on the parameter indicating the first stage of the procedure. Additionally or alternatively, the memory device may read a value of the parameter as part of a power up procedure and may perform a boot procedure using either first data at the boot logical unit or second data at the block of memory based on reading the value of the parameter.

公开(公告)号：US20240184488A1

公开(公告)日：2024-06-06

申请号：US18527041

申请日：2023-12-01

Applicant: Micron Technology, Inc.

Inventor： Marco Onorato ,  Luca Porzio ,  Roberto Izzi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0631 ,  G06F3/0679

Abstract: Methods, systems, and devices for app launch detection from read chunk analysis are described. Read commands may be received for accessing data stored in a memory system. The read commands may be used to determine a distribution of sizes for associated read data over an interval of time based, at least in part, on receiving the read commands. The memory system may detect the launch of an application based in part on the distribution of the sizes of the read data over the interval of time. Upon detecting the launch of the application, a procedure may be performed to reduce a duration associated with launching the application.

公开(公告)号：US11847468B2

公开(公告)日：2023-12-19

申请号：US17645687

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Francesco Basso ,  Luca Porzio ,  Roberto Izzi ,  Francesco Falanga ,  Nadav Grosz ,  Massimo Iaculo

IPC: G06F9/4401 ,  G06F3/06

CPC classification number: G06F9/4406 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0683

Abstract: Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.

公开(公告)号：US11327892B2

公开(公告)日：2022-05-10

申请号：US16893982

申请日：2020-06-05

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F12/0862 ,  G06F12/10 ,  G06F3/06

Abstract: An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.

公开(公告)号：US20220027085A1

公开(公告)日：2022-01-27

申请号：US16937213

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Roberto Izzi ,  Nicola Colella ,  Danilo Caraccio ,  Alessandro Orlando

IPC: G06F3/06 ,  G06F12/06

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

公开(公告)号：US12216525B2

公开(公告)日：2025-02-04

申请号：US18137895

申请日：2023-04-21

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Alessandro Orlando ,  Danilo Caraccio ,  Roberto Izzi

IPC: G06F11/07 ,  G06F11/30

Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.

公开(公告)号：US20240281371A1

公开(公告)日：2024-08-22

申请号：US18586144

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Roberto Izzi ,  Giuseppe Cariello

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/126 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0679 ,  G06F12/126 ,  G06F13/1668 ,  G06F2212/7201 ,  G06F2212/7207

Abstract: Methods, systems, and devices for usage level identification for memory device addresses are described. Systems, techniques, and devices are described herein in which a memory device may determine where to store data according to a level of usage of the data. The memory device may receive a write command indicating data to be written, a type of the data, and a logical address of a memory array for writing the data. The memory device may identify an entry associated with the logical address in a table that maps the logical address to a physical address of the memory array. The entry may include a field configured to maintain a level of usage for the logical address. The memory device may update the level of usage value according to a process and write the data to a physical address of the memory array based on the level of usage value.

公开(公告)号：US11983073B2

公开(公告)日：2024-05-14

申请号：US17874952

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Ferdinando Pascale ,  Roberto Izzi ,  Marco Onorato ,  Erminio Di Martino

IPC: G06F15/177 ,  G06F1/24 ,  G06F9/00 ,  G06F9/4401 ,  G06F11/14

CPC classification number: G06F11/1417 ,  G06F1/24 ,  G06F9/4405

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.