公开(公告)号：US11581056B2

公开(公告)日：2023-02-14

申请号：US17124169

申请日：2020-12-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chiaki Dono ,  Chikara Kondo ,  Roman A. Royer

IPC: G11C29/44 ,  G11C29/48 ,  G11C29/30 ,  G11C29/36 ,  G11C29/12

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

公开(公告)号：US11605416B1

公开(公告)日：2023-03-14

申请号：US17523467

申请日：2021-11-10

Applicant: Micron Technology, Inc.

Inventor： Roman A. Royer

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/22

Abstract: Methods, systems, and devices for reducing duty cycle degradation for a signal path are described. In some examples, a memory system may alternate a polarity of a signal line or signal path that includes a set of transistors during successive active periods of the memory system. In some cases, the memory device may include an inversion control component configured to operate the signal using either a first polarity or a second polarity. The inversion control component may receive an indication when the memory system enters an active period, and may accordingly alternate or the polarity of the signal path during successive active periods. In some examples, the signal path may be coupled with one or more output components which may uninvert signals from the signal path when the inversion control component has inverted the polarity of the signal path.

公开(公告)号：US20210104293A1

公开(公告)日：2021-04-08

申请号：US17124169

申请日：2020-12-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chiaki Dono ,  Chikara Kondo ,  Roman A. Royer

IPC: G11C29/44 ,  G11C29/48 ,  G11C29/36 ,  G11C29/30

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

公开(公告)号：US10937518B2

公开(公告)日：2021-03-02

申请号：US16218267

申请日：2018-12-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Roman A. Royer ,  Chikara Kondo ,  Chiaki Dono

IPC: G11C29/00 ,  G11C29/36 ,  G11C29/12 ,  G11C29/26 ,  G11C5/02 ,  G06F13/16 ,  G11C29/44 ,  G11C29/56

Abstract: Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples. The test interface circuit may be included in a built-in self-test engine or in a standalone tester.

公开(公告)号：US20240330081A1

公开(公告)日：2024-10-03

申请号：US18605006

申请日：2024-03-14

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Nathaniel J. Meier ,  Tomoki Hayashi ,  Roman A. Royer ,  Sean K. Moss ,  Stewart R. Watson

IPC: G06F9/54

CPC classification number: G06F9/542

Abstract: An apparatus including a selectable event reporter internal to a memory device and associated systems and methods are disclosed herein. In some embodiments, the selectable event reporter is dynamically configured to load user-defined event parameters. The selectable event reporter uses the user-defined event parameters to detect corresponding states in command and address signals provided by an external processor. The selectable event reporter communicates the detected events and/or other related observations to an external device.

公开(公告)号：US20210182065A1

公开(公告)日：2021-06-17

申请号：US16715416

申请日：2019-12-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chikara Kondo ,  Roman A. Royer

IPC: G06F9/30 ,  G06F9/38 ,  G06F13/16

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for in-line no operation (NOP) repeat commands. An algorithmic pattern generator (APG) may be loaded with a set of instructions. A line of the instructions may include an active command and an NOP repeat command. The active command may be a command to be provided by the APG when the line of instruction is executed. The NOP repeat command may be a value which indicates a number of times that an NOP command should be issued after the active command when the line of instruction is executed. The APG may include an NOP controller circuit (and/or phase controller circuit) which determines when the next active command should be provided based, in part, on a count of the number of times that an NOP command is issued.

公开(公告)号：US10896738B1

公开(公告)日：2021-01-19

申请号：US16590694

申请日：2019-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chiaki Dono ,  Chikara Kondo ,  Roman A. Royer

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/30 ,  G11C29/36 ,  G11C29/12

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.