公开(公告)号：US20230170013A1

公开(公告)日：2023-06-01

申请号：US17700289

申请日：2022-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Shun Nishimura ,  Yoshinori Matsui

IPC: G11C11/4096 ,  G11C11/4093 ,  H03K19/003

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  H03K19/00384

Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

公开(公告)号：US12237001B2

公开(公告)日：2025-02-25

申请号：US17700289

申请日：2022-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Shun Nishimura ,  Yoshinori Matsui

IPC: G11C11/4096 ,  G11C11/4093 ,  H03K19/003

Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.