公开(公告)号：US12283342B2

公开(公告)日：2025-04-22

申请号：US18055588

申请日：2022-11-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kohei Nakamura ,  Shuichi Tsukada

IPC: G11C7/10 ,  G11C7/02 ,  G11C7/14

Abstract: Apparatuses, systems, and methods for input buffer data feedback equalization (DFE). An input buffer includes a DFE circuit which adjusts a threshold voltage of the input buffer based on a previously latched data bit. The DFE circuit includes a number of DFE legs coupled in parallel to a node of the input buffer. Each DFE leg is selectively activated by a DFE code. Each DFE leg includes a capacitance (e.g., a field effect transistor) which is coupled to the node in an active leg based on the previously latched data bit. The previously latched data bit may also be used to generate a reset signal which couples the capacitors to ground. Each DFE leg may also include a transistor coupled to a bias voltage, which is stable across a range of PVT variations.

公开(公告)号：US11349479B2

公开(公告)日：2022-05-31

申请号：US16273547

申请日：2019-02-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroyuki Matsuno ,  Shuichi Tsukada

IPC: H03K19/00 ,  G11C7/10 ,  H03K19/0185 ,  G11C5/14 ,  G11C7/22 ,  G11C14/00 ,  G11C8/10 ,  G11C11/4093

Abstract: An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.

公开(公告)号：US11176973B2

公开(公告)日：2021-11-16

申请号：US17133480

申请日：2020-12-23

Applicant: Micron Technology, Inc.

Inventor： Hiroyuki Matsuno ,  Shuichi Tsukada

IPC: G11C7/10 ,  G11C11/4091 ,  G11C8/18 ,  G11C11/4074 ,  G11C7/22 ,  G11C7/06 ,  G11C11/4072

Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFB) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFB provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.

公开(公告)号：US10985753B2

公开(公告)日：2021-04-20

申请号：US16229266

申请日：2018-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: H03K17/687 ,  G11C7/12

Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to provide a supply voltage and further includes first and second nodes. An impedance element is coupled between the power supply line and the first node and a first transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. A reference line is configured to provide a reference voltage. A second transistor has a gate, a source coupled to the reference line, and a drain. The gate and the drain of the second transistor are coupled to the gate of the first transistor.

公开(公告)号：US20200257331A1

公开(公告)日：2020-08-13

申请号：US16271679

申请日：2019-02-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: G06F1/08 ,  G06F1/28 ,  H03B5/12

Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

公开(公告)号：US10211832B1

公开(公告)日：2019-02-19

申请号：US15832431

申请日：2017-12-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroyuki Matsuno ,  Shuichi Tsukada

IPC: H03K19/00 ,  G11C5/14 ,  G11C7/10 ,  G11C7/22 ,  G11C14/00 ,  H03K19/0185 ,  G11C8/10

Abstract: An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.

公开(公告)号：US10204666B2

公开(公告)日：2019-02-12

申请号：US15893398

申请日：2018-02-09

Applicant: Micron Technology, Inc.

Inventor： Shuichi Tsukada

IPC: G11C7/10 ,  G11C7/06 ,  G11C11/4093 ,  G11C5/14 ,  G11C7/02 ,  G11C11/4074

Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.

公开(公告)号：US20220011809A1

公开(公告)日：2022-01-13

申请号：US17486429

申请日：2021-09-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: G06F1/08 ,  H03B5/12 ,  G06F1/28

Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

公开(公告)号：US10339988B2

公开(公告)日：2019-07-02

申请号：US16229214

申请日：2018-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shuichi Tsukada

IPC: G11C7/10 ,  G11C7/06 ,  G11C11/4093 ,  G11C5/14 ,  G11C7/02 ,  G11C11/4074

Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.

公开(公告)号：US20150085561A1

公开(公告)日：2015-03-26

申请号：US14495775

申请日：2014-09-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akiko Maeda ,  Shuichi Tsukada ,  Yusuke Jono

IPC: G11C13/00 ,  G11C29/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/005 ,  G11C13/0002 ,  G11C13/004 ,  G11C16/20 ,  G11C29/70 ,  G11C2013/0054 ,  G11C2013/0083 ,  G11C2013/009

Abstract: A semiconductor device includes a memory cell array including a plurality of first and second memory cells each comprising a variable resistance element that establishes an electrical resistance that changes in response to an application of a write voltage after a forming voltage has been applied, the first memory cell to which the forming voltage is applied, and the second memory cell to which the forming voltage is not applied, and the second memory cell being configured to store one of first and second logic values constituting first information, the first and second logic values being different from each other.

Abstract translation: 半导体器件包括存储单元阵列，其包括多个第一和第二存储器单元，每个存储器单元包括可变电阻元件，该可变电阻元件建立响应于在施加形成电压之后施加写入电压而改变的电阻，第一存储器 施加成形电压的单元和不施加形成电压的第二存储单元，并且第二存储单元被配置为存储构成第一信息的第一和第二逻辑值之一，第一和第二逻辑值为 彼此不同。