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公开(公告)号:US20240062840A1
公开(公告)日:2024-02-22
申请号:US17889214
申请日:2022-08-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Michael Winterfeld , Byron D. Harris , Tom Geukens , Juane Li , Fangfang Zhu
CPC classification number: G11C16/3459 , G11C11/5628 , G11C11/5671 , G11C16/10
Abstract: A processing device in a memory sub-system performs a first pass of a multi-pass programming operation to coarsely program a first wordline, performs a second pass to coarsely program a second wordline adjacent to the first wordline, performs a third pass of a multi-pass programming operation to finely program the first wordline, performs a fourth pass of a multi-pass programming operation to coarsely program a third wordline adjacent to the second wordline, performs a fifth pass of a multi-pass programming operation to finely program the second wordline, and responsive to determining that at least the second wordline has been finely programmed, performs a read verify operation on one or more cells associated with the first wordline.
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公开(公告)号:US20200133833A1
公开(公告)日:2020-04-30
申请号:US16171261
申请日:2018-10-25
Applicant: Micron Technology, Inc.
Inventor: Nathan Jared Hughes , Karl D. Schuh , Tom Geukens
IPC: G06F12/02 , G11C16/10 , G06F12/14 , G06F12/1009 , G06F3/06
Abstract: Exemplary methods, apparatuses, and systems include receiving an instruction to atomically write data to a memory component. A plurality of write commands for the first data are generated, including an end of atom indicator. The first plurality of write commands are sent to the memory component while accumulating a plurality of translation table updates corresponding to the write commands One or more translation tables are updated with the plurality of translation table updates in response to determining that the final write command has been successfully sent to the memory component.
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公开(公告)号:US10761978B2
公开(公告)日:2020-09-01
申请号:US16171261
申请日:2018-10-25
Applicant: Micron Technology, Inc.
Inventor: Nathan Jared Hughes , Karl D. Schuh , Tom Geukens
Abstract: Exemplary methods, apparatuses, and systems include receiving an instruction to atomically write data to a memory component. A plurality of write commands for the first data are generated, including an end of atom indicator. The first plurality of write commands are sent to the memory component while accumulating a plurality of translation table updates corresponding to the write commands One or more translation tables are updated with the plurality of translation table updates in response to determining that the final write command has been successfully sent to the memory component.
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