公开(公告)号：US20240111687A1

公开(公告)日：2024-04-04

申请号：US17960006

申请日：2022-10-04

申请人： MIPS Tech, LLC

发明人： James Robinson

IPC分类号： G06F12/1027

CPC分类号： G06F12/1027 ,  G06F2212/681

摘要： In one embodiment, a method includes accessing a virtual address from a request to access a memory of the computing device, where virtual addresses are translated to physical addresses of physical memory in the computing device using an N-level page table, and the lowest level of the page table contains page-table entries specifying the physical address of a frame of physical memory. The method includes searching, using the virtual address, a translation lookaside buffer (TLB) including a plurality of TLB entries, each TLB entry including (1) a tag identifying a virtual address associated with the entry and (2) a page-table entry specifying the physical address of a lower-level page table or of a frame of physical memory associated with the virtual address identified in the tag; and iteratively performing, until the virtual address is translated to a physical address, an address-translation procedure that depends on the cached TLB entries.

公开(公告)号：US10649773B2

公开(公告)日：2020-05-12

申请号：US15092915

申请日：2016-04-07

申请人： MIPS Tech, LLC

发明人： Ranjit J. Rozario ,  Andrew F. Glew ,  Sanjay Patel ,  James Robinson ,  Sudhakar Ranganathan

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0817 ,  G06F12/0811

摘要： A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.