公开(公告)号：US11907542B2

公开(公告)日：2024-02-20

申请号：US18078495

申请日：2022-12-09

申请人： MIPS Tech, LLC

发明人： Sanjay Patel ,  Ranjit J. Rozario

IPC分类号： G06F3/06 ,  G06F12/1027 ,  G06F12/0811 ,  G06F12/0831

CPC分类号： G06F3/0613 ,  G06F3/068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/683

摘要： Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

公开(公告)号：US20240160353A1

公开(公告)日：2024-05-16

申请号：US18409141

申请日：2024-01-10

申请人： MIPS Tech, LLC

发明人： Sanjay Patel ,  Ranjit J. Rozario

IPC分类号： G06F3/06 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/1027

CPC分类号： G06F3/0613 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/068 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/683

摘要： Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

公开(公告)号：US10649773B2

公开(公告)日：2020-05-12

申请号：US15092915

申请日：2016-04-07

申请人： MIPS Tech, LLC

发明人： Ranjit J. Rozario ,  Andrew F. Glew ,  Sanjay Patel ,  James Robinson ,  Sudhakar Ranganathan

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0817 ,  G06F12/0811

摘要： A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.

公开(公告)号：US20180089102A1

公开(公告)日：2018-03-29

申请号：US15824613

申请日：2017-11-28

申请人： MIPS Tech, LLC

发明人： Ranjit J. Rozario ,  Sanjay Patel

IPC分类号： G06F12/1027 ,  G06F12/1045 ,  G06F12/1009 ,  G06F12/0844

CPC分类号： G06F12/1027 ,  G06F12/0844 ,  G06F12/1009 ,  G06F12/1054 ,  G06F2212/652 ,  G06F2212/684 ,  Y02D10/13

摘要： Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support visualization and multi-threading. Disclosed embodiments pertain to a TLB that includes a content addressable memory (CAM) with variable page size entries and a set associative memory with fixed page size entries. The CAM may include: a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets, and each subset comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element (VPE); and a second set of logically contiguous entry locations, distinct from the first set, where the entry locations in the second set may be shared among available VPEs. The set associative memory may comprise a third set of logically contiguous entry locations shared among the available VPEs distinct from the first and second set of entry locations.

公开(公告)号：US10185665B2

公开(公告)日：2019-01-22

申请号：US15824613

申请日：2017-11-28

申请人： MIPS Tech, LLC

发明人： Ranjit J. Rozario ,  Sanjay Patel

IPC分类号： G06F12/10 ,  G06F12/1027 ,  G06F12/0844 ,  G06F12/1045 ,  G06F12/1009

摘要： Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support visualization and multi-threading. Disclosed embodiments pertain to a TLB that includes a content addressable memory (CAM) with variable page size entries and a set associative memory with fixed page size entries. The CAM may include: a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets, and each subset comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element (VPE); and a second set of logically contiguous entry locations, distinct from the first set, where the entry locations in the second set may be shared among available VPEs. The set associative memory may comprise a third set of logically contiguous entry locations shared among the available VPEs distinct from the first and second set of entry locations.