-
1.发明授权Delay locked loop implementation in a synchronous dynamic random access memory 失效在同步动态随机存取存储器中延迟锁定环路的实现公开(公告)号：US08638638B2
公开(公告)日：2014-01-28
申请号：US13732791
申请日：2013-01-02
Applicant: MOSAID Technologies Incorporated
Inventor： Richard C. Foss , Peter B. Gillingham , Graham Allan
IPC: G11C8/00
CPC classification number: G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , H03K5/133 , H03L7/0814
Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。
-
2.发明申请Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory 失效延迟锁定环路在同步动态随机存取存储器中的实现公开(公告)号：US20130121096A1
公开(公告)日：2013-05-16
申请号：US13732791
申请日：2013-01-02
Applicant: MOSAID Technologies Incorporated
Inventor： Richard C. Foss , Peter B. Gillingham , Graham Allan
IPC: G11C7/22
CPC classification number: G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , H03K5/133 , H03L7/0814
Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。
-
3.发明申请Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory 审中-公开延迟锁定环路在同步动态随机存取存储器中的实现公开(公告)号：US20140104969A1
公开(公告)日：2014-04-17
申请号：US14134996
申请日：2013-12-19
Applicant: MOSAID TECHNOLOGIES INCORPORATED
Inventor： Richard C. Foss , Peter B. Gillingham , Graham Allan
IPC: G11C11/4076
CPC classification number: G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , H03K5/133 , H03L7/0814
Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。
-
-
Search Results
3
records
(took 0.015 seconds)
