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    CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
    2.
    发明申请
    CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 有权

    公开(公告)号：US20230046725A1

    公开(公告)日：2023-02-16

    申请号：US17731408

    申请日：2022-04-28

    Applicant: Mosaid Technologies Incorporated

    Inventor： Peter B. Gillingham ,  Graham Allan

    IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/04 ,  G11C14/00

    Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

    Simultaneous read and write data transfer
    4.
    发明授权
    Simultaneous read and write data transfer 有权
    同时读写数据传输

    公开(公告)号：US08898415B2

    公开(公告)日：2014-11-25

    申请号：US13962062

    申请日：2013-08-08

    Applicant: Mosaid Technologies Incorporated

    Inventor： Peter B. Gillingham

    IPC: G06F12/00 ,  G06F3/06 ,  G06F13/42 ,  G06F13/00

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0688 ,  G06F13/4243

    Abstract: A controller for an arrangement of memory devices may issue a write command without waiting for the receipt of a previously issued read command. An addressed memory device may read data out onto the data bus according to a read command while, simultaneously, writing data according to a write command received subsequent to the read command.

    Abstract translation: 用于布置存储器件的控制器可以发出写入命令而不等待先前发出的读取命令的接收。 寻址的存储器件可以根据读取命令将数据读出到数据总线上，同时根据读取命令之后接收的写入命令写入数据。

    High bandwidth memory interface
    5.
    发明授权
    High bandwidth memory interface 有权
    高带宽存储器接口

    公开(公告)号：US08654573B2

    公开(公告)日：2014-02-18

    申请号：US13743794

    申请日：2013-01-17

    Applicant: Mosaid Technologies Incorporated

    Inventor： Peter B. Gillingham ,  Bruce Millar

    IPC: G11C11/00

    CPC classification number: G11C5/06 ,  G06F1/12 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G11C8/18 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device.

    Abstract translation: 一种包括缓冲器和多个同步存储器件的存储器模块。 存储器模块还包括双向总线，并且每个同步存储器件具有双向数据终端。 缓冲器被配置为重新生成在总线上接收的信号以供同步存储器件接收，并且重新产生从任何一个同步存储器装置接收的信号，以便由总线接收。 存储器模块还可以包括命令行和用于经由命令缓冲器向同步存储器件提供命令和时钟信号的时钟线。 存储器模块的组合数据总线宽度可以大于同步存储器件中任何一个的数据总线宽度，并且由存储器模块提供的总地址空间可能大于任何单个同步存储器件的数据空间。

    Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance
    7.
    发明授权
    Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance 有权
    具有多极性位的相变存储器具有增强的耐久性和容错性

    公开(公告)号：US08780622B2

    公开(公告)日：2014-07-15

    申请号：US13860724

    申请日：2013-04-11

    Applicant: Mosaid Technologies Incorporated

    Inventor： Jin-Ki Kim ,  Peter B. Gillingham ,  William F. Petrie

    IPC: G11C11/00 ,  G11C7/10

    CPC classification number: G11C7/1006 ,  G11C13/0004 ,  G11C13/0035 ,  G11C2029/0411 ,  G11C2211/5647

    Abstract: A Phase-Change Memory (PCM) apparatus including a data field for storing a data bits representing a data value or an inversion of the data value and a polarity field for storing a plurality of polarity bits for indicating that the data bits stored in the data field represent the data value or the inversion of the data value. In one embodiment an odd number of set polarity bits indicates that the data bits represent the inversion of the data value and an even number of set polarity bits indicates that the data bits represent the data value. The PCM apparatus has enhanced endurance and improved error tolerance.

    Abstract translation: 一种相变存储器（PCM）装置，包括用于存储表示数据值的数据位或数据值反转的数据位的数据场，以及用于存储用于指示存储在数据中的数据位的多个极性位的极性场 字段表示数据值或数据值的反转。 在一个实施例中，奇数个设置极性位指示数据位表示数据值的反转，偶数个设置的极性位表示数据位表示数据值。 PCM装置具有增强的耐久性和改进的误差容限。

    Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory
    8.
    发明申请
    Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory 失效
    延迟锁定环路在同步动态随机存取存储器中的实现

    公开(公告)号：US20130121096A1

    公开(公告)日：2013-05-16

    申请号：US13732791

    申请日：2013-01-02

    Applicant: MOSAID Technologies Incorporated

    Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

    IPC: G11C7/22

    CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

    Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。

    Clock mode determination in a memory system
    9.
    发明授权
    Clock mode determination in a memory system 有权

    公开(公告)号：US11347396B2

    公开(公告)日：2022-05-31

    申请号：US16950204

    申请日：2020-11-17

    Applicant: Mosaid Technologies Incorporated

    Inventor： Peter B. Gillingham ,  Graham Allan

    IPC: G11C8/00 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/04 ,  G11C14/00 ,  H03K5/00

    Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

    Delay locked loop implementation in a synchronous dynamic random access memory
    10.
    发明授权
    Delay locked loop implementation in a synchronous dynamic random access memory 失效
    在同步动态随机存取存储器中延迟锁定环路的实现

    公开(公告)号：US08638638B2

    公开(公告)日：2014-01-28

    申请号：US13732791

    申请日：2013-01-02

    Applicant: MOSAID Technologies Incorporated

    Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

    IPC: G11C8/00

    CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

    Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。

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