公开(公告)号：US20160181980A1

公开(公告)日：2016-06-23

申请号：US14581337

申请日：2014-12-23

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： ROBERT E. STENGEL ,  NICHOLAS G. CAFARO

IPC: H03B19/14

CPC classification number: H03K3/0315 ,  H03K5/00006

Abstract: Disclosed herein are systems and methods for generating injection-locked, frequency-multiplied output signals. In an embodiment, a circuit includes a ring of a number (N) serially connected delay-buffer elements and an injection-pulse-generation circuit. Each delay-buffer element provides a time delay (D), and at least some of them have at least one pulse-locking injection port. The injection-pulse-generation circuit is configured to transmit balanced-delay injection-pulse signals—that are generated by applying balanced-delay selection logic to a clock signal according to pulse-selection control signals—to the pulse-locking injection ports to provide, at the ring output port, an injection-locked, frequency-multiplied output signal having a frequency that equals the reciprocal of (N*D) and that bears the same proportional relationship to the frequency of the clock signal that the period of the clock signal bears to (N*D).

Abstract translation: 这里公开了用于产生注入锁定倍频输出信号的系统和方法。 在一个实施例中，电路包括数个（N）个串行连接的延迟缓冲元件的环和一个注入脉冲发生电路。 每个延迟缓冲元件提供时间延迟（D），并且它们中的至少一些具有至少一个脉冲锁定注入端口。 注入脉冲发生电路被配置为发送平衡延迟注入脉冲信号，其通过将平衡延迟选择逻辑根据脉冲选择控制信号施加到时钟信号而产生到脉冲锁定注入端口，以提供 在环形输出端口处，具有等于（N * D）的倒数的频率的注入锁定倍频输出信号，并且与时钟信号的频率成比例关系，时钟周期的周期 信号为（N * D）。

公开(公告)号：US20160218754A1

公开(公告)日：2016-07-28

申请号：US14605481

申请日：2015-01-26

Applicant: MOTOROLA SOLUTIONS, INC

Inventor： QICAI SHI ,  NEIYER S. CORREAL ,  JOSEPH P. HECK ,  SPYROS KYPEROUNTAS ,  ROBERT E. STENGEL

IPC: H04B1/04

CPC classification number: H04B1/1036 ,  H04B1/7107 ,  H04J11/0066 ,  H04L25/03821

Abstract: A communication device includes a receiver that is capable of canceling in-channel interference. The receiver includes an antenna for receiving a wireless signal comprising in-channel components and an out-of-channel component, wherein the in-channel components comprise a desired component and an in-channel interference component. A first filter of the receiver filters the wireless signal by blocking at least a portion of the out-of-channel component to produce a first signal comprising the in-channel components, and at least a second filter of the receiver filters the wireless signal by blocking at least a portion of the in-channel components to produce a second signal comprising the out-of-channel component. An in-channel interference estimator of the receiver generates an in-channel interference estimation signal based on the second signal. And a combiner of the filter combines the first signal and the second signal to at least partially cancel the in-channel interference component of the first signal.

公开(公告)号：US20140184289A1

公开(公告)日：2014-07-03

申请号：US13730932

申请日：2012-12-29

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： PAUL H. GAILUS ,  JOSEPH A. CHARASKA ,  STEPHEN B. EINBINDER ,  ROBERT E. STENGEL

IPC: H03L7/08

CPC classification number: H03L7/1974 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/235

Abstract: A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is divided by a fractional-N modulator and divider in the feedback control. The integer loop enables the use of a high frequency reference oscillator that allows a closed loop response of the phase locked loop having a bandwidth that is wider than the modulation bandwidth.

Abstract translation: 用于锁相环频率调制器的单端口调制的方法和装置包括具有压控振荡器（VCO）的锁相环和用于将由分数N调制器分频的VCO的输出相乘的整数循环和 分频器在反馈控制中。 整数循环使得能够使用高频参考振荡器，其允许具有比调制带宽宽的带宽的锁相环的闭环响应。