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公开(公告)号：US20170187767A1
公开(公告)日：2017-06-29
申请号：US15363091
申请日：2016-11-29
发明人： Chun-Chieh Wang
IPC分类号： H04L29/06 , H04L12/707
CPC分类号： H04L65/4076 , H04L45/24 , H04L65/607
摘要： A method for detecting data stream synchronization includes receiving a first data stream, verifying a first data sequence corresponding to a first data sequence field, generating a first flag of successful synchronization verification when the first data sequence is successfully verified, verifying a second data sequence corresponding to a second data sequence field, and generating a second flag of successful synchronization verification when the second data sequence is successfully verified.
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公开(公告)号：US10140209B2
公开(公告)日：2018-11-27
申请号：US15083499
申请日：2016-03-29
发明人： Chun-Chieh Wang
摘要： A time de-interleaving circuit applied to a communication system to de-interleave an interleaved signal is provided. The interleaved signal includes a plurality of cells. The time de-interleaving circuit includes a memory module and a buffering memory module. The memory module stores the cells, which are in a unit of a plurality of cells to form a plurality of cell groups. The memory module is accessed in a unit of one cell group. The buffering memory module buffers a part of the cells from the memory module to arrange an output sequence of the cells.
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公开(公告)号：US20140146928A1
公开(公告)日：2014-05-29
申请号：US14079896
申请日：2013-11-14
发明人： Chun-Chieh Wang , Chun-Jung Chen
IPC分类号： H04B1/10
CPC分类号： H04B1/1081 , H03M13/2732
摘要： A convolutional deinterleaving apparatus includes a memory and a control module. The control module stores a plurality of sets of data into the memory according to a deinterleaving rule. The plurality of sets of data are of a same group. After determining a representative channel state indicator according to an N number of channel state indicators corresponding to an N number of sets of data in the group, the control module stores the representative channel state indicator into the memory. The N number of sets of data of the same group correspond to a same carrier frequency.
摘要翻译： 卷积去交错装置包括存储器和控制模块。 控制模块根据解交织规则将多组数据存储到存储器中。 多组数据是相同的组。 在根据与该组中的N组数据对应的N个信道状态指示符确定代表性信道状态指示符之后，控制模块将代表信道状态指示符存储到存储器中。 相同组的N组数据对应于相同的载波频率。
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4.发明授权Frequency deinterleaving and time deinterleaving circuit, method thereof and receiving circuit of digital television 有权频率去交织和时间解交织电路，数字电视接收电路及其方法公开(公告)号：US09577789B2
公开(公告)日：2017-02-21
申请号：US14624640
申请日：2015-02-18
发明人： Chun-Chieh Wang , Tai-Lai Tung , Ko-Yin Lai , Yi-Ying Liao
IPC分类号： H04N7/173 , H04L1/00 , H04L27/26 , H04N21/434 , H04N21/61 , H04N21/234 , H04N21/44 , H04N21/438
CPC分类号： H04L1/0071 , H04L27/2647 , H04L27/265 , H04N21/23406 , H04N21/434 , H04N21/438 , H04N21/44004 , H04N21/6112
摘要： A receiving circuit for a digital television is provided. The receiving circuit of the digital television, adapted to process a digital television signal to generate transmission data, includes: a front-end circuit, configured to process the digital television signal to generate an interleaved signal; a setting unit, configured to provide a setting value associated with a digital video standard of the digital television signal; a frequency de-interleaving and time de-interleaving circuit, configured to select a frequency de-interleaving scheme and a time de-interleaving scheme corresponding to different digital video standards according to the setting value, and to process the interleaved signal to generate a de-interleaved signal; a quadrature amplitude modulation (QAM) demapping circuit, configured to demap the de-interleaved signal to generate a demapped signal; and a decoder, configured to decode the demapped signal to generate the transmission data.
摘要翻译： 提供了一种用于数字电视的接收电路。 数字电视的接收电路，适于处理数字电视信号以产生传输数据，包括：前端电路，被配置为处理数字电视信号以产生交错信号; 设置单元，被配置为提供与数字电视信号的数字视频标准相关联的设置值; 频率去交织和时间去交织电路，被配置为根据所述设置值选择对应于不同数字视频标准的频率去交织方案和时间去交织方案，并且处理所述交错信号以产生一个de 交错信号 正交幅度调制（QAM）解映射电路，被配置为解映射解码的信号以产生解映射信号; 以及解码器，被配置为解码所解映射的信号以生成所述传输数据。
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5.发明授权Signal processing system and signal processing method cooperating with variable gain amplifier 有权信号处理系统和信号处理方法与可变增益放大器配合使用公开(公告)号：US09444665B2
公开(公告)日：2016-09-13
申请号：US14725678
申请日：2015-05-29
发明人： Yu-Jen Chou , Chun-Chieh Wang , Tai-Lai Tung
CPC分类号： H04L27/08 , H03F3/04 , H03F2200/294 , H03G3/3052 , H04L1/004
摘要： A signal processing system includes a variable gain amplifier, an analog-to-digital converter (ADC), a gain compensation module and a signal processing module. The variable gain amplifier applies a variable gain to an analog input signal to generate an amplified analog signal. The ADC converts the amplified analog signal to an amplified digital signal. The gain compensation module applies a compensation gain to the amplified digital signal to generate a compensated signal. The compensated signal has an instantaneous change lower than a predetermined threshold. The signal processing module performs a signal processing procedure on the compensated signal.
摘要翻译： 信号处理系统包括可变增益放大器，模数转换器（ADC），增益补偿模块和信号处理模块。 可变增益放大器对模拟输入信号施加可变增益以产生放大的模拟信号。 ADC将放大的模拟信号转换为放大的数字信号。 增益补偿模块对放大的数字信号施加补偿增益以产生补偿信号。 补偿信号具有低于预定阈值的瞬时变化。 信号处理模块对补偿信号执行信号处理过程。
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6.发明申请公开(公告)号：US20160164636A1
公开(公告)日：2016-06-09
申请号：US14624640
申请日：2015-02-18
发明人： Chun-Chieh Wang , Tai-Lai Tung , Ko-Yin Lai , Yi-Ying Liao
IPC分类号： H04L1/00 , H04N21/44 , H04N21/61 , H04N21/234 , H04L27/26 , H04N21/434
CPC分类号： H04L1/0071 , H04L27/2647 , H04L27/265 , H04N21/23406 , H04N21/434 , H04N21/438 , H04N21/44004 , H04N21/6112
摘要： A receiving circuit for a digital television is provided. The receiving circuit of the digital television, adapted to process a digital television signal to generate transmission data, includes: a front-end circuit, configured to process the digital television signal to generate an interleaved signal; a setting unit, configured to provide a setting value associated with a digital video standard of the digital television signal; a frequency de-interleaving and time de-interleaving circuit, configured to select a frequency de-interleaving scheme and a time de-interleaving scheme corresponding to different digital video standards according to the setting value, and to process the interleaved signal to generate a de-interleaved signal; a quadrature amplitude modulation (QAM) demapping circuit, configured to demap the de-interleaved signal to generate a demapped signal; and a decoder, configured to decode the demapped signal to generate the transmission data.
摘要翻译： 提供了一种用于数字电视的接收电路。 数字电视的接收电路，适于处理数字电视信号以产生传输数据，包括：前端电路，被配置为处理数字电视信号以产生交错信号; 设置单元，被配置为提供与数字电视信号的数字视频标准相关联的设置值; 频率去交织和时间去交织电路，被配置为根据所述设置值选择对应于不同数字视频标准的频率去交织方案和时间去交织方案，并且处理所述交错信号以产生一个de 交错信号 正交幅度调制（QAM）解映射电路，被配置为解映射解码的信号以产生解映射信号; 以及解码器，被配置为解码所解映射的信号以生成所述传输数据。
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公开(公告)号：US09246526B2
公开(公告)日：2016-01-26
申请号：US14079896
申请日：2013-11-14
发明人： Chun-Chieh Wang , Chun-Jung Chen
CPC分类号： H04B1/1081 , H03M13/2732
摘要： A convolutional deinterleaving apparatus includes a memory and a control module. The control module stores a plurality of sets of data into the memory according to a deinterleaving rule. The plurality of sets of data are of a same group. After determining a representative channel state indicator according to an N number of channel state indicators corresponding to an N number of sets of data in the group, the control module stores the representative channel state indicator into the memory. The N number of sets of data of the same group correspond to a same carrier frequency.
摘要翻译： 卷积去交错装置包括存储器和控制模块。 控制模块根据解交织规则将多组数据存储到存储器中。 多组数据是相同的组。 在根据与该组中的N组数据对应的N个信道状态指示符确定代表性信道状态指示符之后，控制模块将代表信道状态指示符存储到存储器中。 相同组的N组数据对应于相同的载波频率。
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公开(公告)号：US09900201B2
公开(公告)日：2018-02-20
申请号：US15459142
申请日：2017-03-15
发明人： Chun-Chieh Wang
CPC分类号： H04L27/2649 , H03M13/00 , H04L1/0043 , H04L1/0071 , H04L69/22
摘要： A time de-interleaving circuit and a time de-interleaving method perform a time de-interleaving process through writing and reading a plurality of sets of time interleaved data into and from a first memory and a second memory. The time de-interleaving method includes: selecting a set of first time interleaved data and a set of second time interleaved data from the plurality of sets of time interleaved data, the set of first time interleaved data and the set of second time interleaved data having the same delay length; writing the set of first time interleaved data into the first memory; and writing the set of second time interleaved data into the second memory. The first memory utilizes a bit length as an access unit, and the second memory has an access unit smaller than the bit width.
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公开(公告)号：US09148309B2
公开(公告)日：2015-09-29
申请号：US14174007
申请日：2014-02-06
发明人： Chun-Chi Su , Ching-Fu Lan , Chun-Chieh Wang , Tai-Lai Tung , Tung-Sheng Lin
CPC分类号： H04L25/0204 , H04L25/0232
摘要： An apparatus for estimating channel effects is provided. A receiving module receives first data and first reference information arriving in a first time period, second data and second reference data arriving in a second time period, and third data and third reference data arriving in a third time period. An estimation module estimates channel effects corresponding to the first and third data, and the first, second and third reference data, respectively. A coefficient calculation module performs a Wiener filter coefficient calculation on the channel effects corresponding to the first, second and third reference data to generate a set of time-domain interpolation coefficients. An interpolation module interpolates the channel effects corresponding to the first third data according to the set of time-domain interpolation coefficients to generate a channel effect corresponding to the second data.
摘要翻译： 提供了一种用于估计信道效应的装置。 接收模块接收在第一时间段到达的第一数据和第一参考信息，在第二时间段到达的第二数据和第二参考数据，以及在第三时间段到达的第三数据和第三参考数据。 估计模块分别估计与第一和第三数据以及第一，第二和第三参考数据相对应的信道效应。 系数计算模块对与第一，第二和第三参考数据相对应的信道效应执行维纳滤波系数计算，以生成一组时域插值系数。 内插模块根据时域插值系数的集合内插与第一第三数据对应的信道效应，以产生与第二数据相对应的信道效应。
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10.发明授权公开(公告)号：US10164664B2
公开(公告)日：2018-12-25
申请号：US15202954
申请日：2016-07-06
发明人： Chun-Chieh Wang
摘要： A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving.
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