公开(公告)号：US20210082521A1

公开(公告)日：2021-03-18

申请号：US17107692

申请日：2020-11-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ji-Yu HUNG

IPC: G11C16/24 ,  G11C16/26

Abstract: The disclosed technology teaches a memory device with memory cells, each with a sense circuit with an input node in current flow communication, a BLC transistor, a transfer transistor, a current source transistor, and an output circuit to generate data based on a voltage on the sensing node. Also disclosed is a sensing sequence in which control circuits apply BLC voltage to the BLC transistor, transfer voltage to the transfer transistor and current control voltage to the current source transistor to provide a charging current to the BL, and to adjust the current control voltage to provide a keeping current on the BL from the current source transistor, and to apply a read voltage to a selected memory cell on the bit line. Additionally included is applying a timing signal to the output circuit to generate the data based on a voltage on the sensing node.

公开(公告)号：US20210090638A1

公开(公告)日：2021-03-25

申请号：US16581562

申请日：2019-09-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ji-Yu HUNG ,  Shuo-Nan HUNG

IPC: G11C11/4094 ,  G11C11/4093 ,  G11C29/42 ,  G11C29/00

Abstract: A memory device such as a page mode NAND flash, including a page buffer with first and second-level buffer latches is operated using a first pipeline stage, to transfer a page to the first-level buffer latches; a second pipeline stage, to clear the second-level buffer latches to a third buffer level and transfer the page from the first-level buffer latches to the second-level buffer latches; and a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing a second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

公开(公告)号：US20240062833A1

公开(公告)日：2024-02-22

申请号：US17891589

申请日：2022-08-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan HUNG ,  E-Yuan CHANG ,  Ji-Yu HUNG

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/24 ,  G11C16/0483 ,  H03K19/20

Abstract: A memory such as a 3D NAND array, having a page buffer having page buffer cells coupled to bit lines has a search word input such as a search word buffer coupled to word lines. A circuit, such as string select gates, is provided to connect a selected set of memory cells in the array to the page buffer. The page buffer includes sensing circuitry configured to apply a match sense signal to a latch in a plurality of storage elements for a stored data word and an input search word. Logic circuitry uses storage elements in the plurality of storage elements of the page buffer to accumulate the match sense signals output by the sensing circuitry over a sequence matching a plurality stored data words to one or more input search words. A match for a search is based on a threshold and the accumulated match sense signals.

公开(公告)号：US20240233832A1

公开(公告)日：2024-07-11

申请号：US18150594

申请日：2023-01-05

Applicant: Macronix International Co., Ltd.

Inventor： E-Yuan Chang ,  Ji-Yu HUNG

IPC: G11C16/24

CPC classification number: G11C16/24

Abstract: A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.

公开(公告)号：US20200265898A1

公开(公告)日：2020-08-20

申请号：US16278026

申请日：2019-02-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ji-Yu HUNG

IPC: G11C16/24 ,  G11C16/26

Abstract: The disclosed technology teaches a memory device with memory cells, each with a sense circuit with an input node in current flow communication, a BLC transistor, a transfer transistor, a current source transistor, and an output circuit to generate data based on a voltage on the sensing node. Also disclosed is a sensing sequence in which control circuits apply BLC voltage to the BLC transistor, transfer voltage to the transfer transistor and current control voltage to the current source transistor to provide a charging current to the BL, and to adjust the current control voltage to provide a keeping current on the BL from the current source transistor, and to apply a read voltage to a selected memory cell on the bit line. Additionally included is applying a timing signal to the output circuit to generate the data based on a voltage on the sensing node.