公开(公告)号：US11917828B2

公开(公告)日：2024-02-27

申请号：US17314528

申请日：2021-05-07

Applicant: Macronix International Co., Ltd.

Inventor： Ting-Feng Liao ,  Mao-Yuan Weng ,  Kuang-Wen Liu

IPC: H10B41/00 ,  H10B43/50 ,  H01L23/522 ,  H01L21/768 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/50 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/27 ,  H10B43/35

Abstract: Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.

公开(公告)号：US20250107080A1

公开(公告)日：2025-03-27

申请号：US18472229

申请日：2023-09-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Mao-Yuan Weng ,  Ting-Feng Liao ,  Kuang-Wen Liu

IPC: H10B43/27

Abstract: A method of fabricating a memory device at least includes the following steps. A first stack structure is formed above a substrate. The first stack structure includes a plurality of first insulating layers and a plurality of first conductive layers alternately stacked. A top layer of the first stack structure includes a plurality of anti-oxidation atoms therein. A second stack structure is formed on the first stack structure. The second stack structure includes a plurality of second insulating layers and a plurality of middle layers alternately stacked. A slit trench is formed to extend from the second stack structure to a top first conductor layer of the plurality of first conductor layers. A protective layer is formed on a sidewall of the top first conductive layer exposed by the slit trench. The memory device may be a 3D NAND flash memory with high capacity and high performance.

公开(公告)号：US20250098162A1

公开(公告)日：2025-03-20

申请号：US18466820

申请日：2023-09-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Ting-Feng Liao ,  Mao-Yuan Weng ,  Kuang-Wen Liu

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A memory device includes, from bottom to top, a substrate, a laminated layer and a stacked structure. Vertical channel pillars penetrate through the stacked structure and the laminated layer. First isolation structures are disposed aside the vertical channel pillars and penetrate through a lower part of the stacked structure. Second isolation structures are disposed over the first isolation structures and penetrate through an upper part of the stacked structure. Common source lines are disposed aside the vertical channel pillars and penetrate through the stacked structure and part of the laminated layer. From a top view, the common source lines extend in a first direction. Each of the first and second isolation structures has, in the first direction, two wide end portions respectively adjacent to two common source lines. The memory device may be applied in the process of manufacturing a 3D NAND flash memory with high capacity and high performance.