公开(公告)号：US20160232950A1

公开(公告)日：2016-08-11

申请号：US14619810

申请日：2015-02-11

Applicant: Macronix International Co., Ltd.

Inventor： Kuen-Long CHANG ,  Ken-Hui CHEN ,  Ming-Chih HSIEH

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F12/0246 ,  G11C7/1015 ,  G11C7/1045 ,  G11C16/06

Abstract: A memory device includes a memory array and a logic unit communicatively coupled to the memory array. The memory array includes a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The logic unit is configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.

Abstract translation: 存储器件包括存储器阵列和通信地耦合到存储器阵列的逻辑单元。 存储器阵列包括用于存储阵列数据的多个页面和分别对应于用于存储额外数据的多个页面的多个额外阵列。 逻辑单元被配置为接收读取指令，并且以第一访问模式或第二访问模式执行读取操作。 在第一访问模式中，逻辑单元顺序地读出存储在多个页面中的阵列数据。 在第二访问模式下，逻辑单元顺序地读出存储在多个页面中的阵列数据和存储在多个额外阵列中的额外数据。