公开(公告)号：US20140264726A1

公开(公告)日：2014-09-18

申请号：US13920565

申请日：2013-06-18

Applicant: Macronix International Co., Ltd.

Inventor： Yao-Fu Chan ,  Ta-Kang Chu ,  Pi-Shan Tseng

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76229

Abstract: A semiconductor device is provided having reduced corner thinning in a shallow trench isolation (STI) structure of the periphery region. The semiconductor device may be substantially free of any corner thinning at a corner of a STI structure of the periphery region. Methods of manufacturing such a semiconductor device are also provided.

Abstract translation: 提供了一种半导体器件，其具有在外围区域的浅沟槽隔离（STI）结构中具有减小的角部变薄。 半导体器件可以在外围区域的STI结构的拐角处基本上没有任何角部变薄。 还提供了制造这种半导体器件的方法。

公开(公告)号：US20150194314A1

公开(公告)日：2015-07-09

申请号：US14278953

申请日：2014-05-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Ta-Kang Chu ,  Hung-Chi Chen ,  Cheng-Ming Yih

IPC: H01L21/283 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02

CPC classification number: H01L29/41775 ,  H01L21/76897 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7881 ,  H01L29/792

Abstract: A method of fabricating a semiconductor device is provided. A substrate having a first region and a second region is provided. A plurality of stacked gate structures are formed on the substrate of the first region. Each stacked gate structure includes a tunneling dielectric layer, a charge storage layer, an inter-gate dielectric layer, and a control gate. A gap exists between two adjacent stacked gate structures. At least one gate structure is formed on the substrate of the second region. A liner layer is conformally formed on the substrate. A dielectric layer covering the liner layer is formed in the second region. A metal silicide layer is formed on the top portion of the gate structure and on the substrate on both sides of the gate structure. A contact process is performed to form a plurality of contacts connected to the metal silicide layer.

Abstract translation: 提供一种制造半导体器件的方法。 提供具有第一区域和第二区域的衬底。 在第一区域的基板上形成多个堆叠栅极结构。 每个堆叠栅极结构包括隧道介电层，电荷存储层，栅极间电介质层和控制栅极。 在两个相邻的堆叠栅极结构之间存在间隙。 在第二区域的基板上形成至少一个栅极结构。 在衬底上共形形成衬里层。 在第二区域中形成覆盖衬垫层的电介质层。 栅极结构的顶部部分和栅极结构两侧的基板上形成金属硅化物层。 进行接触处理以形成连接到金属硅化物层的多个触点。