公开(公告)号：US20150194314A1

公开(公告)日：2015-07-09

申请号：US14278953

申请日：2014-05-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Ta-Kang Chu ,  Hung-Chi Chen ,  Cheng-Ming Yih

IPC: H01L21/283 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02

CPC classification number: H01L29/41775 ,  H01L21/76897 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7881 ,  H01L29/792

Abstract: A method of fabricating a semiconductor device is provided. A substrate having a first region and a second region is provided. A plurality of stacked gate structures are formed on the substrate of the first region. Each stacked gate structure includes a tunneling dielectric layer, a charge storage layer, an inter-gate dielectric layer, and a control gate. A gap exists between two adjacent stacked gate structures. At least one gate structure is formed on the substrate of the second region. A liner layer is conformally formed on the substrate. A dielectric layer covering the liner layer is formed in the second region. A metal silicide layer is formed on the top portion of the gate structure and on the substrate on both sides of the gate structure. A contact process is performed to form a plurality of contacts connected to the metal silicide layer.

Abstract translation: 提供一种制造半导体器件的方法。 提供具有第一区域和第二区域的衬底。 在第一区域的基板上形成多个堆叠栅极结构。 每个堆叠栅极结构包括隧道介电层，电荷存储层，栅极间电介质层和控制栅极。 在两个相邻的堆叠栅极结构之间存在间隙。 在第二区域的基板上形成至少一个栅极结构。 在衬底上共形形成衬里层。 在第二区域中形成覆盖衬垫层的电介质层。 栅极结构的顶部部分和栅极结构两侧的基板上形成金属硅化物层。 进行接触处理以形成连接到金属硅化物层的多个触点。

公开(公告)号：US10217754B2

公开(公告)日：2019-02-26

申请号：US14278981

申请日：2014-05-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jung Tsai ,  Chun-Lien Su ,  Hsin-Fu Lin ,  Hung-Chi Chen

IPC: H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/66 ,  H01L21/265 ,  H01L29/423 ,  H01L21/762 ,  H01L29/78

Abstract: Provided is a method of fabricating a memory device including performing an ion implantation process by using a mask layer as an implanting mask, so as to form a first embedded doped region and a second embedded doped region in a substrate. The first embedded doped region extends along the first direction, passes through the control gate, and is electrically connected to the first doped region, the second doped region and the third doped region at two sides of control gates. The second embedded doped region extends along the second direction, is located in the substrate under the third doped region, and electrically connected to the third doped region. The first embedded doped region is electrically connected to the second embedded doped region.

公开(公告)号：US20150333077A1

公开(公告)日：2015-11-19

申请号：US14278981

申请日：2014-05-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jung Tsai ,  Chun-Lien Su ,  Hsin-Fu Lin ,  Hung-Chi Chen

IPC: H01L27/115 ,  H01L29/423 ,  H01L21/265 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/42324 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881

Abstract: Provided is a method of fabricating a memory device including performing an ion implantation process by using a mask layer as an implanting mask, so as to form a first embedded doped region and a second embedded doped region in a substrate. The first embedded doped region extends along the first direction, passes through the control gate, and is electrically connected to the first doped region, the second doped region and the third doped region at two sides of control gates. The second embedded doped region extends along the second direction, is located in the substrate under the third doped region, and electrically connected to the third doped region. The first embedded doped region is electrically connected to the second embedded doped region.

Abstract translation: 提供了一种制造存储器件的方法，包括通过使用掩模层作为注入掩模来执行离子注入工艺，以便在衬底中形成第一嵌入掺杂区域和第二嵌入掺杂区域。 第一嵌入式掺杂区域沿着第一方向延伸，通过控制栅极，并且在控制栅极的两侧电连接到第一掺杂区域，第二掺杂区域和第三掺杂区域。 第二嵌入掺杂区域沿着第二方向延伸，位于第三掺杂区域下方的衬底中，并电连接到第三掺杂区域。 第一嵌入式掺杂区域电连接到第二嵌入掺杂区域。