公开(公告)号：US20230240071A1

公开(公告)日：2023-07-27

申请号：US17585150

申请日：2022-01-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Pi-Shan Tseng

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a plurality of barrier structures. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The plurality of barrier structures respectively wrap surfaces of the plurality of gate layers. Each barrier structure includes a first barrier layer and a second barrier layer. The first barrier layer continuously covers a top surface, a bottom surface and a first sidewall of a corresponding gate layer. The second barrier layer covers a second sidewall of the corresponding gate layer opposite to the first sidewall, and connects the first barrier layer. The second barrier layer has a thickness greater than a thickness of the first barrier layer. A method of forming a 3D memory device is also provided.

公开(公告)号：US20140264726A1

公开(公告)日：2014-09-18

申请号：US13920565

申请日：2013-06-18

Applicant: Macronix International Co., Ltd.

Inventor： Yao-Fu Chan ,  Ta-Kang Chu ,  Pi-Shan Tseng

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76229

Abstract: A semiconductor device is provided having reduced corner thinning in a shallow trench isolation (STI) structure of the periphery region. The semiconductor device may be substantially free of any corner thinning at a corner of a STI structure of the periphery region. Methods of manufacturing such a semiconductor device are also provided.

Abstract translation: 提供了一种半导体器件，其具有在外围区域的浅沟槽隔离（STI）结构中具有减小的角部变薄。 半导体器件可以在外围区域的STI结构的拐角处基本上没有任何角部变薄。 还提供了制造这种半导体器件的方法。

公开(公告)号：US20230363159A1

公开(公告)日：2023-11-09

申请号：US17737756

申请日：2022-05-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Pi-Shan Tseng

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: A memory device may be applicated in a 3D AND flash memory device. The memory device includes a gate stack structure, a doped channel stack structure, a source pillar and a drain pillar, and a plurality of dielectric structures. The gate stack structure is located on a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The doped channel stack structure extends through the gate stack structure. The doped channel stack structure includes a plurality of doped channel rings spaced apart from each other. The source pillar and the drain pillar extend through the doped channel stack structure. The source pillar and the drain pillar are respectively electrically connected to the plurality of doped channel rings. The plurality of dielectric structures are located between the plurality of gate layers and the plurality of doped channel rings.

公开(公告)号：US20230077489A1

公开(公告)日：2023-03-16

申请号：US17477267

申请日：2021-09-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Min-Feng Hung ,  Pi-Shan Tseng

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A 3D AND flash memory device includes a gate stack structure, a plurality of channel pillars, a plurality of first conductive pillars and a plurality of second conductive pillars, a plurality of charge storage structures, and a plurality of isolation walls. The gate stack structure is located on a dielectric substrate and includes a plurality of gate layers and a plurality of insulating layers alternately stacked on each other. The channel pillars pass through the gate stack structure. The first conductive pillars and the second conductive pillars are located in the channel pillars and are electrically connected to the channel pillars. The charge storage structures are located between the gate layers and the channel pillar. The isolation walls are buried in the gate layers and cover the charge storage structures at outer sidewalls of the second conductive pillars.

公开(公告)号：US20240268111A1

公开(公告)日：2024-08-08

申请号：US18163299

申请日：2023-02-02

Applicant: MACRONIX International Co., Ltd.

Inventor： Pi-Shan Tseng

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a vertical channel pillar. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The vertical channel pillar penetrates through the stack structure. The vertical channel pillar includes a first source/drain pillar and a channel layer laterally surrounding the first source/drain pillar. The first source/drain pillar includes a first buffer pillar and a first semiconductor layer having a first conductivity type wrapping the first buffer pillar. The channel layer includes a polysilicon layer having a second conductivity type different from the first conductivity type. In some embodiments, the 3D memory device may be, but is not limited to, a AND flash memory.

公开(公告)号：US20230363160A1

公开(公告)日：2023-11-09

申请号：US17737771

申请日：2022-05-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Meng-Yen Wu ,  Pi-Shan Tseng

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/522 ,  H01L23/04

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/5283 ,  H01L23/5226 ,  H01L23/04

Abstract: A memory device may be applicated in a 3D AND flash memory device. The memory device includes a dielectric substrate, a plurality of memory cells, a slit structure, and a middle section of a seal ring. The gate composite stack structure disposed on the dielectric substrate in a first region and a second region of the dielectric substrate. The plurality of memory cells disposed in the composite stack structure. The slit structure extends through the composite stack structure in first region. The composite stack structure is divided into a plurality of blocks. The middle section of a seal ring extends through the composite stack structure in the second region. The middle section of the seal ring includes a body part extending through the composite stack structure in the second region and a liner layer located between the body part and the composite stack structure.