公开(公告)号：US09412425B2

公开(公告)日：2016-08-09

申请号：US14673530

申请日：2015-03-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

公开(公告)号：US20150206557A1

公开(公告)日：2015-07-23

申请号：US14673530

申请日：2015-03-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/08 ,  G11C7/12 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器，接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号，包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组，并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器，并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。

公开(公告)号：US09001604B2

公开(公告)日：2015-04-07

申请号：US13801500

申请日：2013-03-13

Applicant: Macronix International Co., Ltd.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/08 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器，接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号，包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组，并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器，并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。

公开(公告)号：US20140269125A1

公开(公告)日：2014-09-18

申请号：US13801500

申请日：2013-03-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/06

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器，接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号，包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组，并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器，并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。