公开(公告)号：US20160267995A1

公开(公告)日：2016-09-15

申请号：US14643907

申请日：2015-03-10

Applicant: Macronix International Co., Ltd.

Inventor： Kuo-Pin CHANG ,  Hang-Ting LUE ,  Wen-Wei YEH

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3472

Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset of the set of word lines in the selected block to induce tunneling in memory cells coupled to the selected subset. Word line-side inhibit voltages are applied to an unselected subset of the set of word lines in the selected block to inhibit tunneling in memory cells coupled to the unselected subset.

Abstract translation: 提供了一种用于操作包括多个存储单元块的NAND阵列的方法。 存储单元块包括多个具有第一串选择开关和第二串选择开关之间的通道线的NAND串。 多个NAND串在第一和第二串选择开关之间共享一组字线。 通道侧擦除电压通过所选块中的第一串选择开关施加到通道线。 字线侧擦除电压被施加到所选块中所选择的字线集合的选定子集，以诱导耦合到所选子集的存储器单元中的隧穿。 字线侧抑制电压被施加到所选块中的字线组的未选择子集，以抑制耦合到未选择子集的存储器单元中的隧穿。