公开(公告)号：US20160284413A1

公开(公告)日：2016-09-29

申请号：US14668728

申请日：2015-03-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin CHANG

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483

Abstract: A method of operating a NAND array including blocks of memory cells is provided. A block includes a plurality of strings having channel lines between first and second string select switches. The strings share a set of word lines between the first and second string select switches. A channel-side voltage can be applied to the channel lines . A control voltage can be applied to a selected subset of the first string select switches. The channel lines can be floated at ends of the second string select switches. Tunneling in memory cells coupled to an unselected subset of the first string select switches can be inhibited. Word line-side erase voltages can be applied to word lines in the set of word lines in the block to induce tunneling in memory cells coupled to the word lines and coupled to the selected subset of the first string select switches.

Abstract translation: 提供了一种操作包括存储单元块的NAND阵列的方法。 块包括在第一和第二串选择开关之间具有通道线的多个串。 字符串在第一和第二字符串选择开关之间共享一组字线。 通道侧电压可以施加到通道线。 可以将控制电压施加到第一串选择开关的选定子集。 通道线可以浮在第二串选择开关的端部。 可以抑制耦合到第一串选择开关的未选择子集的存储器单元中的隧道化。 字线侧擦除电压可以被施加到块中的字线集合中的字线，以在耦合到字线的存储器单元中感应隧道并耦合到所选择的第一串选择开关的子集。

公开(公告)号：US20200328154A1

公开(公告)日：2020-10-15

申请号：US16380040

申请日：2019-04-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei JIANG ,  Kuo-Pin CHANG ,  Chih-Wei HU

IPC: H01L23/528 ,  H01L21/768 ,  H01L27/11568 ,  H01L21/311 ,  H01L21/28 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11582

Abstract: Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.

公开(公告)号：US20200335510A1

公开(公告)日：2020-10-22

申请号：US16387650

申请日：2019-04-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei JIANG ,  Kuo-Pin CHANG ,  Chieh-Fang CHEN

IPC: H01L27/1158 ,  H01L29/417 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.

公开(公告)号：US20160267995A1

公开(公告)日：2016-09-15

申请号：US14643907

申请日：2015-03-10

Applicant: Macronix International Co., Ltd.

Inventor： Kuo-Pin CHANG ,  Hang-Ting LUE ,  Wen-Wei YEH

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3472

Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset of the set of word lines in the selected block to induce tunneling in memory cells coupled to the selected subset. Word line-side inhibit voltages are applied to an unselected subset of the set of word lines in the selected block to inhibit tunneling in memory cells coupled to the unselected subset.

Abstract translation: 提供了一种用于操作包括多个存储单元块的NAND阵列的方法。 存储单元块包括多个具有第一串选择开关和第二串选择开关之间的通道线的NAND串。 多个NAND串在第一和第二串选择开关之间共享一组字线。 通道侧擦除电压通过所选块中的第一串选择开关施加到通道线。 字线侧擦除电压被施加到所选块中所选择的字线集合的选定子集，以诱导耦合到所选子集的存储器单元中的隧穿。 字线侧抑制电压被施加到所选块中的字线组的未选择子集，以抑制耦合到未选择子集的存储器单元中的隧穿。

公开(公告)号：US20160049201A1

公开(公告)日：2016-02-18

申请号：US14668790

申请日：2015-03-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Kuo-Pin CHANG

IPC: G11C16/14

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/16 ,  G11C2216/18 ,  H01L27/11551 ,  H01L27/11578

Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.

Abstract translation: 提供了一种用于操作包括多个存储单元块的NAND阵列的方法。 多个块中的存储单元块包括在第一串选择开关和第二串选择开关之间具有通道线的多个NAND串。 多个NAND串在第一和第二串选择开关之间共享一组字线。 通道侧擦除电压通过所选块中的第一串选择开关施加到通道线。 字线侧擦除电压被施加到所选择的子集，包括由所选择的块中的NAND串共享的一组字线中的一个以上的成员，以在耦合到所选子集的存储器单元中诱发隧穿，同时在存储器单元中禁止隧道 耦合到包括该组字线的多于一个成员的未选择子集。