公开(公告)号：US5751162A

公开(公告)日：1998-05-12

申请号：US659990

申请日：1996-06-07

申请人： Mahesh Mehendale ,  Shivaling Mahant-Shetti ,  Manisha Agarwala ,  Mark G. Harward ,  Robert J. Landers

发明人： Mahesh Mehendale ,  Shivaling Mahant-Shetti ,  Manisha Agarwala ,  Mark G. Harward ,  Robert J. Landers

IPC分类号： H03K19/173

CPC分类号： H03K19/1737

摘要： A logic module 400 for use in a field programmable gate array 100 can be selectively reconfigured to perform over 2,200 boolean combinational functions on output 431, to operate as a full adder with sum and carry outputs, or to perform the sequential function of a D latch or a D flipflop. Logic module 400 is comprised of 2-input multiplexers 500 and 600 which are used to form both the combinational and sequential circuits, thereby efficiently utilizing space on gate array 100.

摘要翻译： 可以选择性地重新配置用于现场可编程门阵列100的逻辑模块400，以在输出端431上执行2200多个布尔组合函数，以作为具有和和和进位输出的全加器运行，或执行D锁存器的顺序功能 或D触发器。 逻辑模块400由用于组合组合电路和顺序电路的2输入多路复用器500和600组成，从而有效利用门阵列100上的空间。

公开(公告)号：US5488315A

公开(公告)日：1996-01-30

申请号：US369060

申请日：1995-01-05

申请人： Shivaling S. Mahant-Shetti ,  Manisha Agarwala ,  Mahesh M. Mehendale ,  Robert J. Landers ,  Mark G. Harward

发明人： Shivaling S. Mahant-Shetti ,  Manisha Agarwala ,  Mahesh M. Mehendale ,  Robert J. Landers ,  Mark G. Harward

IPC分类号： G06F7/50 ,  G06F7/501 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F7/501 ,  H03K19/1736 ,  G06F2207/4812

摘要： An adder-based base cell (10) is provided for field programmable gate arrays. The base cell (10) includes a first inverter (13) operable to receive a first input signal (A). A first NAND gate (12) is coupled to the first inverter (13) and is operable to receive a second input signal (B). A first 2:1 multiplexer (14) is coupled to the first NAND gate (12) and is operable to receive a third input signal (C). The output of the first 2:1 multiplexer (14) represents a first function (F1). A second inverter (17) is operable to receive a fourth input signal (D). A second NAND gate (16) is coupled to the second inverter (17) and is operable to receive a fifth input signal (E). An XOR gate (18) is coupled to the second NAND gate (16), is operable to receive a sixth input signal (F), and is coupled to the first 2:1 multiplexer (14). The output of the XOR gate represents a partial sum function (PS.sub.-- 1). A second 2:1 multiplexer (19) is operable to receive a seventh input signal (G), is operable to receive an eighth input signal (H) and is coupled to the XOR gate (18). The output of the second 2:1 multiplexer (19) represents a second function (F2).

摘要翻译： 为现场可编程门阵列提供基于加法器的基电池（10）。 基站（10）包括可操作以接收第一输入信号（A）的第一反相器（13）。 第一NAND门（12）耦合到第一反相器（13）并且可操作以接收第二输入信号（B）。 第一2：1多路复用器（14）耦合到第一与非门（12）并且可操作以接收第三输入信号（C）。 第一2：1多路复用器（14）的输出表示第一功能（F1）。 第二逆变器（17）可操作以接收第四输入信号（D）。 第二NAND门（16）耦合到第二反相器（17）并且可操作以接收第五输入信号（E）。 XOR门（18）耦合到第二与非门（16），可操作以接收第六输入信号（F），并耦合到第一2:1复用器（14）。 XOR门的输出表示部分和函数（PS-1）。 第二2:1复用器（19）可操作以接收第七输入信号（G），可操作以接收第八输入信号（H）并耦合到异或门（18）。 第二2:1复用器（19）的输出表示第二功能（F2）。

公开(公告)号：US07925687B2

公开(公告)日：2011-04-12

申请号：US11383335

申请日：2006-05-15

申请人： Manisha Agarwala ,  John M. Johnsen ,  Lewis Nardini

发明人： Manisha Agarwala ,  John M. Johnsen ,  Lewis Nardini

IPC分类号： G06F7/38

CPC分类号： G06F11/261

摘要： A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.

摘要翻译： 饱和计数将接收的事件信号计数到第一预定数量。 溢出计数器计数溢出到第二预定数量。 当溢出计数达到第二个预定数量时，计数器指示溢出计数不为零并饱和，并以最大计数停止计数。 可以通过寄存器读取操作读取计数器。 第一预定位数和第二预定位数之和为8位的整数倍的总和。

公开(公告)号：US07702498B2

公开(公告)日：2010-04-20

申请号：US11383339

申请日：2006-05-15

申请人： Manisha Agarwala

发明人： Manisha Agarwala

IPC分类号： G06F9/455 ,  G06F9/45

CPC分类号： G06F11/3656 ,  G06F11/3636

摘要： A method of tracing data processor activity includes trace data markers indicating initiation and termination of at least one trace function at a specified program counter address and emulation pause related markers indicating initiation and termination of an emulation halt state at a specified program counter. Each emulation pause related marker includes a conflict bit indicating the presence or absence of a simultaneous trace data marker having a different program counter address.

摘要翻译： 跟踪数据处理器活动的方法包括指示指定程序计数器地址处的至少一个跟踪功能的启动和终止的跟踪数据标记，以及指示在指定程序计数器处的仿真停止状态的启动和终止的仿真暂停相关标记。 每个仿真暂停相关标记包括指示存在或不存在具有不同程序计数器地址的同时跟踪数据标记的冲突位。

公开(公告)号：US07475172B2

公开(公告)日：2009-01-06

申请号：US11566751

申请日：2006-12-05

申请人： Lewis Nardini ,  Manisha Agarwala ,  John M. Johnsen

发明人： Lewis Nardini ,  Manisha Agarwala ,  John M. Johnsen

IPC分类号： G06F3/00 ,  G06F13/12 ,  G06F9/455 ,  G01R31/28

CPC分类号： G06F11/3636 ,  G06F11/3476

摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.

摘要翻译： 本发明通过将当前跟踪地址的各个字节与存储的先前跟踪地址进行比较来提供跟踪地址压缩。 只有当前跟踪地址中与存储的先前跟踪地址不匹配或者比当前跟踪地址中与存储的先前跟踪地址不匹配的任何部分不太重要的最低有效字节被传送。 这有时会减少需要传输的数据量。 如果存在完全不匹配，则可以使用当前跟踪地址更新先前的跟踪地址。

公开(公告)号：US07237151B2

公开(公告)日：2007-06-26

申请号：US10729639

申请日：2003-12-05

申请人： Gary L. Swoboda ,  Bryan Thome ,  Manisha Agarwala

发明人： Gary L. Swoboda ,  Bryan Thome ,  Manisha Agarwala

IPC分类号： G06F11/30 ,  G06F11/34

CPC分类号： G06F11/261

摘要： When a RESET signal is generated in a target processor during a test procedure, a reset sync marker is generated in a program counter trace stream. The reset sync marker includes a plurality of packets, the packets identifying that the reset sync marker is the result of a RESET signal. The packets identify the program counter address at the time of the generation of the RESET signal and relate the reset sync marker to a timing trace stream. When the RESET signal is removed, a second (reset-off) sync marker is generated identifying the removal of the RESET signal, identifying the program counter address, and relating the second sync marker to the timing trance stream.

摘要翻译： 当在测试过程中在目标处理器中产生RESET信号时，在程序计数器跟踪流中产生复位同步标记。 复位同步标记包括多个分组，该分组标识复位同步标记是RESET信号的结果。 分组在生成RESET信号时识别程序计数器地址，并将复位同步标记与定时跟踪流相关联。 当RESET信号被去除时，产生识别RESET信号的去除，识别程序计数器地址以及将第二同步标记与定时恍惚流相关联的第二（复位）同步标记。

公开(公告)号：US07225365B2

公开(公告)日：2007-05-29

申请号：US10729326

申请日：2003-12-05

申请人： Gary L. Swoboda ,  Bryan Thome ,  Manisha Agarwala

发明人： Gary L. Swoboda ,  Bryan Thome ,  Manisha Agarwala

IPC分类号： G06F11/00

CPC分类号： G06F11/3672

摘要： When a NEW SECONDARY CODE EXECUTION START POINT signal is generated in a target processor during a test procedure after the return from an interrupt service routine (i.e., an original secondary code sequence), a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of the NEW SECONDARY CODE EXECUTION START POINT signal. The new secondary program code start point sync marker identifies the absolute program counter address at the time of the generation of the NEW SECONDARY CODE EXECUTION START POINT signal and relates the NEW SECONDARY CODE EXECUTION START POINT signal sync marker to a timing trace stream.

摘要翻译： 在从中断服务程序（即，原始的次要代码序列）返回之后的测试过程期间在目标处理器中产生新的二级代码执行开始点信号时，在程序计数器跟踪流中生成同步标记。 同步标记包括多个分组，作为新的二级代码执行开始点信号的结果，识别出同步标记的分组已经被生成。 新的二级程序代码起始点同步标记识别生成新的二级代码执行开始点信号时的绝对程序计数器地址，并将新的二级代码执行开始点信号同步标记与定时跟踪流相关联。

公开(公告)号：US20070100599A1

公开(公告)日：2007-05-03

申请号：US11563821

申请日：2006-11-28

申请人： Manisha Agarwala ,  Maria Gill ,  John Johnsen

发明人： Manisha Agarwala ,  Maria Gill ,  John Johnsen

IPC分类号： G06F9/455

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO. It is possible that for a specific stream, the length and fields of the data that should be exported vary. This invention is a scheme to send out only the relevant fields.

摘要翻译： 生成跟踪目标处理器活动的数据流。 当多个流打开时，它们会在不同的时间被写入其各自的FIFO。 对于特定的流，可能导出的数据的长度和字段可能不同。 本发明是仅发出相关领域的方案。

公开(公告)号：US20070055855A1

公开(公告)日：2007-03-08

申请号：US11359158

申请日：2006-02-21

申请人： Manisha Agarwala ,  Lewis Nardini

发明人： Manisha Agarwala ,  Lewis Nardini

IPC分类号： G06F15/177

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.

公开(公告)号：US20070011662A1

公开(公告)日：2007-01-11

申请号：US11383337

申请日：2006-05-15

申请人： Manisha Agarwala ,  Bryan Thome ,  John Johnsen ,  Gary Swoboda ,  Lewis Nardini ,  Maria Gill

发明人： Manisha Agarwala ,  Bryan Thome ,  John Johnsen ,  Gary Swoboda ,  Lewis Nardini ,  Maria Gill

IPC分类号： G06F9/44

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.

摘要翻译： 在数据处理器中跟踪程序计数器活动的方法周期性地发送包括当前程序计数器地址的程序计数器同步点。 在同步点之间，程序计数器地址由相对于最后一个程序计数器同步点的程序计数器偏移指示。 程序计数器偏移作为整数个预定位数的部分发送。 程序计数器的同步点经常被传送到足够多的程序计数器偏移量至少比程序计数器地址少一个部分。