公开(公告)号：US5414736A

公开(公告)日：1995-05-09

申请号：US925673

申请日：1992-08-07

申请人： Makoto Hasegawa ,  Kazuaki Takahashi ,  Masahiro Mimura ,  Kazunori Watanabe ,  Katsushi Yokozaki ,  Hiroyuki Harada

发明人： Makoto Hasegawa ,  Kazuaki Takahashi ,  Masahiro Mimura ,  Kazunori Watanabe ,  Katsushi Yokozaki ,  Hiroyuki Harada

IPC分类号： H04L27/152 ,  H03D3/00

CPC分类号： H04L27/152

摘要： An FSK data receiving system is provided which is capable of constituting a direct-conversion receiver suitable for realizing an integrated circuit, is capable of decoding in a wide receiving band width, and is capable of realizing a small-sized and less-electric power consumption data receiving. An FSK-modulated local oscillator signal 3 is applied to a local oscillator 2, and there is provided a decode circuit 15 which obtains the decode signal 14 by judging whether the FSK-modulated frequency deviation of the carrier wave signal 1 is a positive deviation or a negative deviation on the basis of a comparison result of a voltage change in a frequency-voltage conversion circuit 16 for a base-band signal 8; i.e. the output signal of a frequency mixer 6. An offset amount of the local oscillator frequency is judged by a voltage judging circuit 17 to produce a control signal 18 Further, there is provided another decode circuit 22 which makes a judgement of frequency change of the base-band signal 8 and a judgement of in-phase/opposite-phase relationship from the decode signal 14 and the output of the voltage judging circuit 17 so as to obtain a decode signal 23. Moreover, there is provided a decode signal processing circuit 25 which obtains a decode signal 24 from the decode signals 14, 23 in response to the control signal 18.

摘要翻译： 提供一种FSK数据接收系统，其能够构成适合于实现集成电路的直接转换接收机，能够以宽的接收带宽进行解码，并且能够实现小型和小电力的功耗 数据接收。 FSK调制的本地振荡器信号3被施加到本地振荡器2，并且提供了解码电路15，其通过判断载波信号1的FSK调制的频率偏差是正偏差来获得解码信号14，或者 基于用于基带信号8的频率 - 电压转换电路16中的电压变化的比较结果的负偏差; 即混频器6的输出信号。本地振荡器频率的偏移量由电压判断电路17判定，以产生控制信号18。另外，还提供另一个解码电路22， 基带信号8和来自解码信号14和电压判断电路17的输出的同相/反相位关系的判断，以获得解码信号23.此外，提供了一种解码信号处理电路 25，其响应于控制信号18从解码信号14,23获得解码信号24。

公开(公告)号：US5293408A

公开(公告)日：1994-03-08

申请号：US942183

申请日：1992-09-09

申请人： Kazuaki Takahashi ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Yasumi Imagawa ,  Hiroyuki Harada ,  Masahiro Mimura ,  Yasuaki Namura

发明人： Kazuaki Takahashi ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Yasumi Imagawa ,  Hiroyuki Harada ,  Masahiro Mimura ,  Yasuaki Namura

IPC分类号： H04B1/30 ,  H04L27/152 ,  H04B1/10

CPC分类号： H04B1/30 ,  H04L27/152

摘要： A data receiving system comprising an I base-band signal and a Q base-band signal which are used in a quadrature demodulation operation. Zero-crossing points of respective base-band signals are detected and a control signal is generated in response to each zero-crossing point. A phase-shift switching circuit alternately selects either the I base-band signal or the Q base-band signal in response to the control signal to generate an I/Q base-band signal. And, a demodulation operation is executed on the basis of the I/Q signal.

摘要翻译： 一种数据接收系统，包括在正交解调操作中使用的I基带信号和Q基带信号。 检测各基带信号的过零点，并响应于每个过零点产生控制信号。 相移切换电路响应于控制信号交替地选择I基带信号或Q基带信号以产生I / Q基带信号。 并且，基于I / Q信号执行解调操作。

公开(公告)号：US06236690B1

公开(公告)日：2001-05-22

申请号：US09332078

申请日：1999-06-14

申请人： Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Hiroyuki Harada ,  Takaaki Kishigami ,  Yasunari Tanaka

发明人： Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Hiroyuki Harada ,  Takaaki Kishigami ,  Yasunari Tanaka

IPC分类号： H04L2714

CPC分类号： H04B1/30 ,  H03D3/007 ,  H04B17/318

摘要： A direct-conversion receiver includes a local oscillator for generating a local oscillator signal, a converter circuit for converting a received radio signal into a pair of a baseband I signal and a baseband Q signal in response to the local oscillator signal, a demodulator for demodulating the pair of the baseband I signal and the baseband Q signal into a demodulation-resultant signal which is neither an I signal nor a Q signal, a detector circuit for detecting a difference between a frequency of the local oscillator signal and a frequency of a carrier of the received radio signal, a clock signal generator for generating a first clock signal providing a timing which corresponds to a center of a symbol period, a signal delay device for delaying the first clock signal to provide a second clock signal, and a symbol deciding circuit for deciding a logic state of the demodulation-resultant signal at a timing determined by the second clock signal.

摘要翻译： 一种直接转换接收机，包括用于产生本地振荡器信号的本地振荡器，用于响应于本地振荡器信号将接收到的无线电信号转换为一对基带I信号和基带Q信号的转换器电路，用于解调的解调器 一对基带I信号和基带Q信号转换成既不是I信号也不是Q信号的解调结果信号，用于检测本地振荡器信号的频率和载波频率之间的差异的检测器电路 接收的无线电信号的时钟信号发生器，用于产生提供对应于符号周期的中心的定时的第一时钟信号的时钟信号发生器，用于延迟第一时钟信号以提供第二时钟信号的信号延迟装置，以及符号决定 电路，用于在由第二时钟信号确定的定时处决定解调结果信号的逻辑状态。

公开(公告)号：US5617451A

公开(公告)日：1997-04-01

申请号：US302982

申请日：1994-09-12

申请人： Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Hiroyuki Harada ,  Takaaki Kishigami ,  Yasunari Tanaka

发明人： Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Hiroyuki Harada ,  Takaaki Kishigami ,  Yasunari Tanaka

IPC分类号： H03D3/00 ,  H04B1/30 ,  H04B17/00 ,  H03D1/00

CPC分类号： H04B1/30 ,  H03D3/007 ,  H04B17/318

摘要： A direct-conversion receiver includes a direct-conversion demodulator. A first device detects a strength of a received signal. A clock signal generator outputs a clock signal in response to a reception start signal. The clock signal has a frequency corresponding to a symbol rate or higher. A second device samples an output signal of the demodulator at a timing determined by the clock signal. A third device samples an output signal of the first device at a timing determined by the clock signal. A fourth device stores "n" output signals of the second device which relate to a signal periodically transmitted from a transmitting station "n" times, wherein "n" denotes a natural number equal to 2 or greater. A fifth device stores "n" output signals of the third device which correspond in timing to the "n" output signals of the second device. A sixth device reads out signals from the fourth device, and reads out signals from the fifth device. The sixth device weights the signals read out from the fourth device in response to the signals read out from the fifth device. A seventh device combines output signals of the sixth device.

摘要翻译： 直接转换接收机包括直接转换解调器。 第一设备检测接收信号的强度。 时钟信号发生器响应于接收开始信号输出时钟信号。 时钟信号具有对应于符号率或更高的频率。 第二设备在由时钟信号确定的定时处对解调器的输出信号进行采样。 第三设备在由时钟信号确定的定时采样第一设备的输出信号。 第四设备存储与从发送站“n”周期性地发送的信号相关的第二设备的“n”个输出信号，其中“n”表示等于2或更大的自然数。 第五装置将与定时对应的第三装置的“n”个输出信号存储到第二装置的“n”个输出信号。 第六设备从第四设备读出信号，并从第五设备读出信号。 响应于从第五装置读出的信号，第六装置对从第四装置读出的信号进行加权。 第七设备组合第六设备的输出信号。

公开(公告)号：US5450032A

公开(公告)日：1995-09-12

申请号：US209140

申请日：1994-03-11

申请人： Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Hiroyuki Harada

发明人： Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Hiroyuki Harada

IPC分类号： H04B1/26 ,  H04L27/14 ,  H04L27/152

CPC分类号： H04L27/152

摘要： A first demodulator for generating a demodulated signal by demodulating first and second baseband signals obtained from a received frequency shift keying signal, comprises: a first mixer for mixing the first baseband signal with the second baseband signal; a frequency divider for 1/2-frequency-dividing an output of the first mixer; a second mixer for mixing the first baseband signal with an output of said frequency divider; and a frequency judging circuit for judging whether or not a frequency of an output of the second mixer is larger than a reference value to generate the demodulated signal. In order to effect the frequency judging by the frequency judging circuit always at a high frequency, there may be further provided a first inverter after the first mixer, a second inverter after the frequency judging circuit for compensating the inverting of the first inverter, and a frequency comparing circuit for detecting the frequency of the output of the first mixer. In order to effect the frequency judging on the second baseband signal side, third and fourth mixers may be further provided. The frequency judging are made from the first baseband signal and the second baseband signal.

摘要翻译： 一种用于通过解调从接收的频移键控信号获得的第一和第二基带信号来产生解调信号的第一解调器，包括：第一混频器，用于混合第一基带信号与第二基带信号; 用于对所述第一混频器的输出进行1/2分频的分频器; 第二混频器，用于将第一基带信号与所述分频器的输出混频; 以及频率判定电路，用于判断第二混频器的输出频率是否大于参考值，以产生解调信号。 为了总是以高频率进行频率判定电路的频率判定，还可以在第一混频器之后设置第一反相器，频率判定电路之后的第二反相器补偿第一反相器的反相，以及 频率比较电路，用于检测第一混频器的输出频率。 为了实现第二基带信号侧的频率判定，可以进一步提供第三和第四混频器。 从第一基带信号和第二基带信号进行频率判定。

公开(公告)号：US5640428A

公开(公告)日：1997-06-17

申请号：US555407

申请日：1995-11-09

申请人： Katsuaki Abe ,  Masahiro Mimura ,  Makoto Hasegawa ,  Kazunori Watanabe ,  Katsushi Yokozaki

发明人： Katsuaki Abe ,  Masahiro Mimura ,  Makoto Hasegawa ,  Kazunori Watanabe ,  Katsushi Yokozaki

IPC分类号： H04L27/152 ,  H03D3/00 ,  H04L27/14

CPC分类号： H04L27/1525

摘要： In a first direct conversion receiver for demodulating I and Q signals, having a quadrature relation therebetween, obtained from a received FSK signal through a direct conversion, a first D FF latches a level of the I signal when a sign condition of I and Q signals moves from the same to different sign conditions, a second D FF latches a level of the Q signal when the sign condition of the I and Q signals moves from the different to same sign condition and EXCLUSIVE OR operations are made among the I and Q signals and the outputs of the first and second D FFs to provide a frequent data judgement to improve a receiving sensitivity of an FSK signal having a relative low modulation index. In a second direct conversion receiver, a sign change in the Q signal is detected by a first edge detection circuit 17, a first D FF holds the level of the I signal, and an EXCLUSIVE OR circuit provides a first demodulation result. A sign change in the I signal is detected by a second edge detection circuit 17, a second D FF holds the level of the Q signal, an EXCLUSIVE OR circuit provides a second demodulation result and a subtracting circuit combines the first and second demodulation results. An earlier change detection circuit also combines the first and second demodulation results with a delay in the first and second demodulation results reduced.

摘要翻译： 在用于通过直接转换从接收的FSK信号获得的具有正交关系的用于解调I和Q信号的第一直接转换接收机中，当I和Q信号的符号条件时，第一D FF锁存I信号的电平 从相同状态移动到不同的符号状态，当I和Q信号的符号条件从不同的符号状态移动到相同的符号条件时，第二D FF锁存Q信号的电平，并且在I和Q信号之间进行EXCLUSIVE OR运算 以及第一和第二D FF的输出以提供频繁的数据判断，以提高具有相对较低调制指数的FSK信号的接收灵敏度。 在第二直接变换接收机中，Q信号的符号改变由第一边缘检测电路17检测，第一D FF保持I信号的电平，并且EXCLUSIVE OR电路提供第一解调结果。 I信号的符号变化由第二边缘检测电路17检测，第二D FF保持Q信号的电平，EXCLUSIVE OR电路提供第二解调结果，减法电路组合第一和第二解调结果。 较早的改变检测电路还将第一和第二解调结果与减少的第一和第二解调结果中的延迟相结合。

公开(公告)号：US5781588A

公开(公告)日：1998-07-14

申请号：US548373

申请日：1995-11-01

申请人： Katsuaki Abe ,  Takaaki Kishigami ,  Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Yoichi Yamaki ,  Toshiyuki Tsumura ,  Hiroshi Katayama

发明人： Katsuaki Abe ,  Takaaki Kishigami ,  Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Yoichi Yamaki ,  Toshiyuki Tsumura ,  Hiroshi Katayama

IPC分类号： H03G3/20 ,  H04L25/06 ,  H04L27/14

CPC分类号： H03G3/3068 ,  H04L25/061

摘要： An FSK signal receiver includes an amplifier which amplifies a first FSK signal at an adjustable gain. A frequency converter converts an output signal from the amplifier into a second FSK signal having a frequency lower than a frequency of the first FSK signal. A demodulator demodulates the second FSK signal into a baseband signal. A bit-state detector detects a bit state from the baseband signal in response to a threshold. A calculator calculates a number of times of occurrence of a fact that the baseband signal moves across the threshold during a given time. The gain of the amplifier is adjusted in response to the number of times which is calculated by the calculator.

公开(公告)号：US5987075A

公开(公告)日：1999-11-16

申请号：US988209

申请日：1997-12-10

申请人： Katsuaki Abe ,  Takaaki Kishigami ,  Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Yoichi Yamaki ,  Toshiyuki Tsumura ,  Hiroshi Katayama

发明人： Katsuaki Abe ,  Takaaki Kishigami ,  Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki ,  Yoichi Yamaki ,  Toshiyuki Tsumura ,  Hiroshi Katayama

IPC分类号： H03G3/20 ,  H04L25/06 ,  H04L27/14

CPC分类号： H03G3/3068 ,  H04L25/061

摘要： An FSK signal receiver includes an amplifier which amplifies a first FSK signal at an adjustable gain. A frequency converter converts an output signal from the amplifier into a second FSK signal having a frequency lower than a frequency of the first FSK signal. A demodulator demodulates the second FSK signal into a baseband signal. A bit-state detector detects a bit state from the baseband signal in response to a threshold. A calculator calculates a number of times of occurrence of a fact that the baseband signal moves across the threshold during a given time. The gain of the amplifier is adjusted in response to the number of times which is calculated by the calculator.

摘要翻译： FSK信号接收机包括放大器，其以可调增益放大第一FSK信号。 变频器将来自放大器的输出信号转换成具有低于第一FSK信号的频率的频率的第二FSK信号。 解调器将第二FSK信号解调为基带信号。 位状态检测器响应于阈值从基带信号检测比特状态。 计算器计算在给定时间内基带信号在阈值上移动的事实的发生次数。 响应于由计算器计算的次数来调节放大器的增益。

公开(公告)号：US5633898A

公开(公告)日：1997-05-27

申请号：US360648

申请日：1994-12-21

申请人： Takaaki Kishigami ,  Katsuaki Abe ,  Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki

发明人： Takaaki Kishigami ,  Katsuaki Abe ,  Masahiro Mimura ,  Makoto Hasegawa ,  Katsushi Yokozaki

IPC分类号： H04L27/152 ,  H04L27/14 ,  H03D3/18 ,  H04L27/06 ,  H04L27/10

CPC分类号： H04L27/1525

摘要： A first AFC apparatus receives and detects I and Q signals from a received first FSK signal with a local osc signal; demodulates the I and Q signals; F/V-converts I or/and Q signals into a voltage; compares it with a reference; and detects a frequency deviation direction of the local osc signal from the carrier signal according to the results of comparing and the demodulating. The local osc frequency is controlled by a given amount according to the result of the frequency deviation direction detection. A second AFC apparatus receives and detects I and Q signals using a first osc signal; FSK-modulates the I and Q signals with a second local osc signal having a lower frequency than the first local osc signal; and compares the frequency of the second FSK signal and the second local osc signal to supply a demodulation result. A frequency control for the first local osc signal is obtained by an averaging circuit averaging the modulation result. The F/V converter used in this apparatus has various modification and amplitude limiter may be provided as necessary. The averaging may be effected for a given data period of the first FSK signal. Power consumption can be reduced by selectively supplying a power with/without a holing circuit. FSK receivers use these automatic frequency control apparatus are also disclosed.

摘要翻译： 第一AFC设备接收并检测来自接收到的具有本地osc信​​号的第一FSK信号的I和Q信号; 解调I和Q信号; 将I /或Q信号F / V转换为电压; 将其与参考进行比较; 并且根据比较结果和解调来检测来自载波信号的本地振荡信号的频率偏差方向。 根据频偏方向检测的结果，本地振荡频率由给定量控制。 第二AFC设备使用第一osc信号接收和检测I和Q信号; FSK调制具有比第一本地osc信​​号低的频率的第二本地振荡信号的I和Q信号; 并且比较第二FSK信号和第二本地osc信​​号的频率以提供解调结果。 通过对调制结果进行平均的平均电路来获得第一局部振荡信号的频率控制。 该装置中使用的F / V转换器具有各种修改，并且可以根据需要提供幅度限制器。 对于第一FSK信号的给定数据周期可以进行平均。 通过有选择地提供带有/不带有孔的电路的电力可以降低功耗。 FSK接收机使用这些自动频率控制装置也被公开。

公开(公告)号：US5448774A

公开(公告)日：1995-09-05

申请号：US229109

申请日：1994-04-18

申请人： Katsushi Yokozaki ,  Yasumi Imagawa

发明人： Katsushi Yokozaki ,  Yasumi Imagawa

IPC分类号： H04B1/18 ,  H03G3/20 ,  H04L27/14 ,  H04Q7/18 ,  H04B1/16

CPC分类号： H03G3/3068

摘要： A direct conversion type FSK receiver has an intermittent reception mode and includes a detecting and holding device in a low frequency unit and a gain control device in a high frequency unit. The receiver starts a reception operation in response to an intermittent reception control signal and controls the gain of the high frequency unit based on the detection of the received signal strength level before an interval of time during which the receiver receives a signal transmitted for the receiver and maintains the controlled gain for that interval of time. As a result, the receiver has reduced reception disturbance, which disturbance is due to intermodulation occurring when a large input signal is received.

摘要翻译： 直接转换型FSK接收机具有间歇接收模式，并且包括低频单元中的检测和保持装置以及高频单元中的增益控制装置。 接收机响应于间歇接收控制信号开始接收操作，并且基于在接收机接收到针对接收机发送的信号的时间间隔之前的接收信号强度电平的检测来控制高频单元的增益，以及 维持该时间间隔的可控增益。 结果，接收机具有减少的接收干扰，该干扰是由于当接收到大的输入信号时发生互调。