摘要:
A direct-conversion receiver includes a local oscillator for generating a local oscillator signal, a converter circuit for converting a received radio signal into a pair of a baseband I signal and a baseband Q signal in response to the local oscillator signal, a demodulator for demodulating the pair of the baseband I signal and the baseband Q signal into a demodulation-resultant signal which is neither an I signal nor a Q signal, a detector circuit for detecting a difference between a frequency of the local oscillator signal and a frequency of a carrier of the received radio signal, a clock signal generator for generating a first clock signal providing a timing which corresponds to a center of a symbol period, a signal delay device for delaying the first clock signal to provide a second clock signal, and a symbol deciding circuit for deciding a logic state of the demodulation-resultant signal at a timing determined by the second clock signal.
摘要:
A direct-conversion receiver includes a direct-conversion demodulator. A first device detects a strength of a received signal. A clock signal generator outputs a clock signal in response to a reception start signal. The clock signal has a frequency corresponding to a symbol rate or higher. A second device samples an output signal of the demodulator at a timing determined by the clock signal. A third device samples an output signal of the first device at a timing determined by the clock signal. A fourth device stores "n" output signals of the second device which relate to a signal periodically transmitted from a transmitting station "n" times, wherein "n" denotes a natural number equal to 2 or greater. A fifth device stores "n" output signals of the third device which correspond in timing to the "n" output signals of the second device. A sixth device reads out signals from the fourth device, and reads out signals from the fifth device. The sixth device weights the signals read out from the fourth device in response to the signals read out from the fifth device. A seventh device combines output signals of the sixth device.
摘要:
An FSK signal receiver includes an amplifier which amplifies a first FSK signal at an adjustable gain. A frequency converter converts an output signal from the amplifier into a second FSK signal having a frequency lower than a frequency of the first FSK signal. A demodulator demodulates the second FSK signal into a baseband signal. A bit-state detector detects a bit state from the baseband signal in response to a threshold. A calculator calculates a number of times of occurrence of a fact that the baseband signal moves across the threshold during a given time. The gain of the amplifier is adjusted in response to the number of times which is calculated by the calculator.
摘要:
An FSK signal receiver includes an amplifier which amplifies a first FSK signal at an adjustable gain. A frequency converter converts an output signal from the amplifier into a second FSK signal having a frequency lower than a frequency of the first FSK signal. A demodulator demodulates the second FSK signal into a baseband signal. A bit-state detector detects a bit state from the baseband signal in response to a threshold. A calculator calculates a number of times of occurrence of a fact that the baseband signal moves across the threshold during a given time. The gain of the amplifier is adjusted in response to the number of times which is calculated by the calculator.
摘要:
A first AFC apparatus receives and detects I and Q signals from a received first FSK signal with a local osc signal; demodulates the I and Q signals; F/V-converts I or/and Q signals into a voltage; compares it with a reference; and detects a frequency deviation direction of the local osc signal from the carrier signal according to the results of comparing and the demodulating. The local osc frequency is controlled by a given amount according to the result of the frequency deviation direction detection. A second AFC apparatus receives and detects I and Q signals using a first osc signal; FSK-modulates the I and Q signals with a second local osc signal having a lower frequency than the first local osc signal; and compares the frequency of the second FSK signal and the second local osc signal to supply a demodulation result. A frequency control for the first local osc signal is obtained by an averaging circuit averaging the modulation result. The F/V converter used in this apparatus has various modification and amplitude limiter may be provided as necessary. The averaging may be effected for a given data period of the first FSK signal. Power consumption can be reduced by selectively supplying a power with/without a holing circuit. FSK receivers use these automatic frequency control apparatus are also disclosed.
摘要:
A first demodulator for generating a demodulated signal by demodulating first and second baseband signals obtained from a received frequency shift keying signal, comprises: a first mixer for mixing the first baseband signal with the second baseband signal; a frequency divider for 1/2-frequency-dividing an output of the first mixer; a second mixer for mixing the first baseband signal with an output of said frequency divider; and a frequency judging circuit for judging whether or not a frequency of an output of the second mixer is larger than a reference value to generate the demodulated signal. In order to effect the frequency judging by the frequency judging circuit always at a high frequency, there may be further provided a first inverter after the first mixer, a second inverter after the frequency judging circuit for compensating the inverting of the first inverter, and a frequency comparing circuit for detecting the frequency of the output of the first mixer. In order to effect the frequency judging on the second baseband signal side, third and fourth mixers may be further provided. The frequency judging are made from the first baseband signal and the second baseband signal.
摘要:
An FSK data receiving system is provided which is capable of constituting a direct-conversion receiver suitable for realizing an integrated circuit, is capable of decoding in a wide receiving band width, and is capable of realizing a small-sized and less-electric power consumption data receiving. An FSK-modulated local oscillator signal 3 is applied to a local oscillator 2, and there is provided a decode circuit 15 which obtains the decode signal 14 by judging whether the FSK-modulated frequency deviation of the carrier wave signal 1 is a positive deviation or a negative deviation on the basis of a comparison result of a voltage change in a frequency-voltage conversion circuit 16 for a base-band signal 8; i.e. the output signal of a frequency mixer 6. An offset amount of the local oscillator frequency is judged by a voltage judging circuit 17 to produce a control signal 18 Further, there is provided another decode circuit 22 which makes a judgement of frequency change of the base-band signal 8 and a judgement of in-phase/opposite-phase relationship from the decode signal 14 and the output of the voltage judging circuit 17 so as to obtain a decode signal 23. Moreover, there is provided a decode signal processing circuit 25 which obtains a decode signal 24 from the decode signals 14, 23 in response to the control signal 18.
摘要:
A data receiving system comprising an I base-band signal and a Q base-band signal which are used in a quadrature demodulation operation. Zero-crossing points of respective base-band signals are detected and a control signal is generated in response to each zero-crossing point. A phase-shift switching circuit alternately selects either the I base-band signal or the Q base-band signal in response to the control signal to generate an I/Q base-band signal. And, a demodulation operation is executed on the basis of the I/Q signal.
摘要:
In a first direct conversion receiver for demodulating I and Q signals, having a quadrature relation therebetween, obtained from a received FSK signal through a direct conversion, a first D FF latches a level of the I signal when a sign condition of I and Q signals moves from the same to different sign conditions, a second D FF latches a level of the Q signal when the sign condition of the I and Q signals moves from the different to same sign condition and EXCLUSIVE OR operations are made among the I and Q signals and the outputs of the first and second D FFs to provide a frequent data judgement to improve a receiving sensitivity of an FSK signal having a relative low modulation index. In a second direct conversion receiver, a sign change in the Q signal is detected by a first edge detection circuit 17, a first D FF holds the level of the I signal, and an EXCLUSIVE OR circuit provides a first demodulation result. A sign change in the I signal is detected by a second edge detection circuit 17, a second D FF holds the level of the Q signal, an EXCLUSIVE OR circuit provides a second demodulation result and a subtracting circuit combines the first and second demodulation results. An earlier change detection circuit also combines the first and second demodulation results with a delay in the first and second demodulation results reduced.
摘要:
A mobile television receiver includes a TV tuner demodulating an incoming TV signal into a first video signal. A first horizontal sync signal is separated from the first video signal. Detection is made as to a quality of an image represented by the first video signal. A second horizontal sync signal is generated. Detection is made as to a difference between a phase of the first horizontal sync signal and a phase of the second horizontal sync signal. The phase of the second horizontal sync signal is controlled in response to the detected phase difference between the first horizontal sync signal and the second horizontal sync signal so that the second horizontal sync signal will be locked in phase and frequency to the first horizontal sync signal. A memory unit stores the first video signal in response to a memory control signal, and outputs the stored first video signal as a second video signal. The memory control signal is generated in response to the detected image quality. The second video signal is displayed in response to the second horizontal sync signal.