公开(公告)号：US08514640B2

公开(公告)日：2013-08-20

申请号：US13036525

申请日：2011-02-28

申请人： Makoto Miakashi ,  Katsuaki Isobe ,  Noboru Shibata

发明人： Makoto Miakashi ,  Katsuaki Isobe ,  Noboru Shibata

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3436

摘要： A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and the third bit lines and the second sense amplifier, and connect the second and the third bit lines to the second sense amplifier.

摘要翻译： 一种半导体存储器件，其中可以减少相邻单元之间的干扰并且可以抑制芯片面积的扩大，其包括：存储单元阵列，其中连接到多个字线和多个位线的多个存储器单元被布置在矩阵中 形成; 读出放大器中的每一个将连接到每个位线; 控制电路，其控制字线和位线的电压，并将数据编程到存储器单元中或从存储器单元读取数据; 其中所述多个位线至少包括彼此相邻的第一，第二，第三和第四位线，并且所述读出放大器至少包括第一和第二读出放大器，第一和第四选择晶体管是 设置在第一和第四位线与第一读出放大器之间，并将第一和第四位线连接到第一读出放大器; 以及设置在第二和第三位线和第二读出放大器之间的第二和第三选择晶体管，并将第二和第三位线连接到第二读出放大器。

公开(公告)号：US20110238889A1

公开(公告)日：2011-09-29

申请号：US12884648

申请日：2010-09-17

申请人： Makoto Miakashi ,  Noboru Shibata

发明人： Makoto Miakashi ,  Noboru Shibata

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3436

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array is composed of a plurality of memory cells arranged in a matrix pattern. The control circuit sets a first flag data in a second memory cell in order to write data to a plurality of first memory cells of memory cell array, the second memory cell having been selected at the same time as the first memory cells, determines whether the first flag data is set in the second memory cell before data is read from the first memory cells, and reads no data from the first memory cells and outputs data of first logic level if the first flag data is not set in the second memory cell, and reads data from the first memory cells if the first flag data is set in the second memory cell.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列由以矩阵图案排列的多个存储单元组成。 控制电路在第二存储器单元中设置第一标志数据，以便将数据写入存储单元阵列的多个第一存储单元，第二存储单元已经与第一存储器单元同时被选择， 在从第一存储器单元读取数据之前，在第二存储单元中设置第一标志数据，并且如果第一标志数据未被设置在第二存储器单元中，则不从第一存储器单元读取数据并输出第一逻辑电平的数据， 并且如果第一标志数据被设置在第二存储器单元中，则从第一存储器单元读取数据。