公开(公告)号：US08395922B2

公开(公告)日：2013-03-12

申请号：US13035134

申请日：2011-02-25

申请人： Mitsuhiro Noguchi ,  Kenji Sawamura ,  Takeshi Kamigaichi ,  Katsuaki Isobe

发明人： Mitsuhiro Noguchi ,  Kenji Sawamura ,  Takeshi Kamigaichi ,  Katsuaki Isobe

IPC分类号： G11C5/06

CPC分类号： G11C5/025 ,  G11C16/0483 ,  G11C16/26

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal. At least one of a width of each of the plurality of second interconnects along a second direction perpendicular to the first direction and a thickness of each of the plurality of second interconnects along a third direction perpendicular to the first direction and the second direction is set smaller than each of the plurality of first interconnects, and the first sense amplifier circuit and the second sense amplifier circuit are disposed to face each other across the memory cell array.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，第一读出放大器电路和第二读出放大器电路。 存储单元阵列包括多个第一存储单元单元，多个第二存储单元单元，多个第一互连和多个第二互连。 第一读出放大器电路连接到多个第一互连。 第二读出放大器电路连接到多个第二互连。 互连上表面的高度相等。 沿着与第一方向垂直的第二方向的多个第二互连件的每一个的宽度中的至少一个以及沿着垂直于第一方向和第二方向的第三方向的多个第二互连件中的每一个的厚度被设置得较小 并且第一读出放大器电路和第二读出放大器电路被设置为跨越存储单元阵列彼此面对。

公开(公告)号：US08315094B2

公开(公告)日：2012-11-20

申请号：US12957865

申请日：2010-12-01

申请人： Kazushige Kanda ,  Toshiki Hisada ,  Katsuaki Isobe

发明人： Kazushige Kanda ,  Toshiki Hisada ,  Katsuaki Isobe

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.

摘要翻译： 提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于 低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

公开(公告)号：US08300466B2

公开(公告)日：2012-10-30

申请号：US13037965

申请日：2011-03-01

申请人： Hiroshi Maejima ,  Katsuaki Isobe

发明人： Hiroshi Maejima ,  Katsuaki Isobe

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.

摘要翻译： 读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电 位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中 高于所述接地电位，并且等于或低于所述第二电压。

公开(公告)号：US08295090B2

公开(公告)日：2012-10-23

申请号：US12817697

申请日：2010-06-17

申请人： Katsuaki Isobe ,  Noboru Shibata ,  Toshiki Hisada

发明人： Katsuaki Isobe ,  Noboru Shibata ,  Toshiki Hisada

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/1095

摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

摘要翻译： 根据一个实施例，形成在衬底中的第一导电类型的第一阱。 第二导电类型的第二阱形成在第一阱中。 多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是 布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

公开(公告)号：US20120201070A1

公开(公告)日：2012-08-09

申请号：US13415953

申请日：2012-03-09

申请人： Hiroshi Maejima ,  Katsuaki Isobe ,  Hideo Mukai

发明人： Hiroshi Maejima ,  Katsuaki Isobe ,  Hideo Mukai

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C7/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor storage device includes first and second intersecting wires; a electrically rewritable memory cell disposed at each intersection of the first second wires, including a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire to a standby voltage larger than a reference voltage prior to programming a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying to the selected first wire a program voltage for programming of the selected variable resistor and applying to the non-selected second wire a control voltage which prevents the rectifying device from turning ON.

摘要翻译： 非易失性半导体存储装置包括第一和第二相交线; 在第一第二导线的交点设置有包含用于将电阻值作为数据非易失性地存储的可变电阻器和整流装置的电可重写存储单元串联连接; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。 在通过将参考电压提供给未选择的第一线和所选择的第二线之前，控制电路将未选择的第二线预充电至大于参考电压的待机电压，然后再对连接到所选择的第一和第二线的可变电阻进行编程， 向所选择的第一线施加用于对所选择的可变电阻器进行编程的编程电压，并向未选择的第二线施加防止整流装置导通的控制电压。

公开(公告)号：US07978517B2

公开(公告)日：2011-07-12

申请号：US12719686

申请日：2010-03-08

申请人： Katsuaki Isobe

发明人： Katsuaki Isobe

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C16/0483

摘要： A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of the memory cell units having a plurality of electrically rewritable memory cells that are connected to each other, wherein a bit line that is selected by a sense amplifier is charged in a state where a drain-side select gate line, a source-side select gate line and a p-type semiconductor substrate are set at a ground potential, and source lines, n-type wells, p-type wells, and a bit line that is not selected by the sense amplifier are in a floating state.

摘要翻译： 在选择的位线和非选择的位线彼此相邻时读取的NAND快闪存储器具有存储单元阵列，其具有多个块，每个块由多个存储单元单元组成，每个块由多个存储单元单元组成 所述存储单元单元具有彼此连接的多个电可重写存储单元，其中由读出放大器选择的位线在漏极侧选择栅极线，源极侧选择栅极 线路和p型半导体衬底设置为接地电位，源极线，n型阱，p型阱和未被读出放大器选择的位线处于浮置状态。

公开(公告)号：US07800935B2

公开(公告)日：2010-09-21

申请号：US12252675

申请日：2008-10-16

申请人： Hiroshi Maejima ,  Katsuaki Isobe ,  Naoya Tokiwa ,  Satoru Takase ,  Yasuyuki Fukuda ,  Hideo Mukai ,  Tsuneo Inaba

发明人： Hiroshi Maejima ,  Katsuaki Isobe ,  Naoya Tokiwa ,  Satoru Takase ,  Yasuyuki Fukuda ,  Hideo Mukai ,  Tsuneo Inaba

IPC分类号： G11C11/00

CPC分类号： G11C13/0009 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2211/5642 ,  G11C2213/11 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/72

摘要： A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0 ΔR2.

摘要翻译： 一种包括存储单元的电阻变化存储器件，所述存储器单元具有具有高电阻值的稳定状态并且以非易失性方式存储这样的多电平数据：至少三个电阻值R0，R1和R2（R0 < R1 ＆Dgr; R2的关系。

公开(公告)号：US07760549B2

公开(公告)日：2010-07-20

申请号：US12204409

申请日：2008-09-04

申请人： Katsuaki Isobe ,  Noboru Shibata

发明人： Katsuaki Isobe ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/32 ,  G11C2211/565

摘要： A memory device includes a control circuit which controls a semiconductor region, a first bit line, a second bit line and a source line. The control circuit is comprised of means for making the first bit line floating, after pre-charging the first bit line to a first potential, means for varying the first bit line from the first potential to a third potential by providing a second potential to the second bit line, the semiconductor region and the source line with the first bit line in the floating state, and means for reading data of the first cell transistor to the first bit line, after setting the first bit line to the third potential.

摘要翻译： 存储器件包括控制半导体区域，第一位线，第二位线和源极线的控制电路。 所述控制电路包括用于在将所述第一位线预充电到第一电位之后使所述第一位线浮置的装置，用于通过向所述第一电位提供第二电位来将所述第一位线从所述第一电位改变到第三电位的装置 第二位线，半导体区域和处于浮置状态的第一位线的源极线，以及在将第一位线设置为第三电位之后，将第一单元晶体管的数据读取到第一位线的装置。

公开(公告)号：US20100097860A1

公开(公告)日：2010-04-22

申请号：US12642503

申请日：2009-12-18

申请人： Hiroshi MAEJIMA ,  Katsuaki Isobe

发明人： Hiroshi MAEJIMA ,  Katsuaki Isobe

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.

摘要翻译： 读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电 位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中 高于所述接地电位，并且等于或低于所述第二电压。

公开(公告)号：US20100097832A1

公开(公告)日：2010-04-22

申请号：US12580795

申请日：2009-10-16

申请人： Hideo MUKAI ,  Hiroshi Maejima ,  Katsuaki Isobe

发明人： Hideo MUKAI ,  Hiroshi Maejima ,  Katsuaki Isobe

IPC分类号： G11C11/00 ,  G11C5/02 ,  G11C5/06

CPC分类号： G11C8/14 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/72

摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

摘要翻译： 一种非易失性半导体存储器件，包括具有以矩阵形式设置的多个MAT（单位阵列）的单元阵列，所述MAT各包括多条第一线，与第一线交叉的多条第二线，以及 存储单元连接在第一和第二线之间。 该装置还包括第一和第二驱动电路，选择连接到每个MAT的存储器单元的第一和第二线，所述存储器单元被访问，并且驱动所选择的第一和第二行来写入或读取数据。 存储单元通过连接到从MAT中选择的每个第一行形成页面。 该设备还包括以页为单位锁存写入或读取数据的数据锁存器，其中第一和第二驱动电路多次驱动第一和第二行以写入或读取单元阵列中的一页的数据。