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    Method and system for optimizing code using an optimizing coprocessor
    1.
    发明授权
    Method and system for optimizing code using an optimizing coprocessor 失效
    使用优化协处理器优化代码的方法和系统

    公开(公告)号：US06820254B2

    公开(公告)日：2004-11-16

    申请号：US09681327

    申请日：2001-03-19

    申请人： Jack Robert Smith ,  Sebastian Theodore Ventrone

    发明人： Jack Robert Smith ,  Sebastian Theodore Ventrone

    IPC分类号： G06F945

    CPC分类号： G06F8/443

    摘要： A data processing system includes a central processing unit (CPU) in communication with a system memory. Within the system memory, there is stored legacy code that does not utilize the full features of the CPU. The data processing system also includes a code-optimizing coprocessor in communication with the CPU and the system memory. Control logic within the code-optimizing coprocessor causes the code-optimizing coprocessor to generate optimized code from the legacy code at the same time the CPU executes the legacy code, such that the optimized code is tailored according to the CPU. After the code-optimizing coprocessor has generated at least some optimized code, the code-optimizing coprocessor causes the CPU to automatically utilize at least some optimized code in lieu of at least some of the legacy code.

    摘要翻译： 数据处理系统包括与系统存储器通信的中央处理单元（CPU）。 在系统内存中，存储了不利用CPU全部功能的旧版代码。 数据处理系统还包括与CPU和系统存储器通信的代码优化协处理器。 代码优化协处理器内的控制逻辑使得代码优化协处理器在CPU执行遗留代码的同时从旧代码生成优化的代码，使得优化的代码根据CPU进行调整。 在代码优化协处理器已经生成了至少一些优化的代码之后，代码优化协处理器使CPU自动利用至少一些优化的代码来代替至少一些遗留代码。

    Coding of FPGA and standard cell logic in a tiling structure
    2.
    发明授权
    Coding of FPGA and standard cell logic in a tiling structure 失效
    FPGA和标准单元逻辑在平铺结构中的编码

    公开(公告)号：US07080344B2

    公开(公告)日：2006-07-18

    申请号：US10604071

    申请日：2003-06-25

    申请人： Stanislav Peter Bajuk ,  Jack Robert Smith ,  Sebastian Theodore Ventrone

    发明人： Stanislav Peter Bajuk ,  Jack Robert Smith ,  Sebastian Theodore Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5068

    摘要： A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect's type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

    摘要翻译： 一种存储和修改寄存器传输语言（RTL）的方法和系统，描述逻辑类型。 在声明信号互连时，基于信号互连的类型，为信号互连定义了寄存器传输语言的语言扩展。 语言扩展允许不同的信号互连类型，例如与现场可编程门阵列（FPGA）和标准单元一起使用的信号互连类型存储在相同的文件阵列层次结构中。 这种存储有助于改变逻辑类型，从而最终导致集成电路（IC）更小（使用更多标准单元）或更灵活（使用更多的FPGA单元）。 在物理设计周期内执行从一个RTL类型到另一个RTL类型的转换，其中在掩蔽最终芯片设计之前执行组件（信息）的布线，定时和布局。

    Method and apparatus for reducing power consumption of a processing integrated circuit
    3.
    发明授权
    Method and apparatus for reducing power consumption of a processing integrated circuit 失效
    用于降低处理集成电路的功耗的方法和装置

    公开(公告)号：US06834353B2

    公开(公告)日：2004-12-21

    申请号：US09682816

    申请日：2001-10-22

    申请人： Jack Robert Smith ,  Sebastian Theodore Ventrone

    发明人： Jack Robert Smith ,  Sebastian Theodore Ventrone

    IPC分类号： G06F132

    CPC分类号： G06F1/3203

    摘要： In a first aspect, a method is provided for conserving power in a processing integrated circuit. The method includes the steps of (1) calculating power consumption for executing an instruction and data corresponding to the instruction; and (2) executing the instruction if such execution does not exceed a predetermined power level. In a second aspect, a method is provided for conserving power in a processing integrated circuit employing a plurality of execution units. The method includes the steps of (1) comparing a total power to be consumed by the processing integrated circuit to a power budget for the processing integrated circuit; and (2) if the total power exceeds the power budget, freezing execution of an instruction by one of the plurality of execution units so as to allow execution of the instruction to continue at a later time from where execution was frozen. Numerous other aspects are provided, as are systems and apparatus.

    摘要翻译： 在第一方面，提供了一种用于在处理集成电路中节省功率的方法。 该方法包括以下步骤：（1）计算用于执行指令的功耗和对应于该指令的数据; 和（2）如果这样的执行不超过预定功率电平，则执行指令。 在第二方面，提供一种用于在采用多个执行单元的处理集成电路中节省功率的方法。 该方法包括以下步骤：（1）将由处理集成电路消耗的总功率与处理集成电路的功率预算进行比较; 以及（2）如果总功率超过功率预算，则冻结多个执行单元之一的指令的执行，以便允许执行指令在执行被冻结的较后时间继续。 还提供了许多其他方面，系统和装置也是如此。

    Stacked voltage rails for low-voltage DC distribution
    5.
    发明授权
    Stacked voltage rails for low-voltage DC distribution 失效
    用于低压直流分配的堆叠电压轨

    公开(公告)号：US06479974B2

    公开(公告)日：2002-11-12

    申请号：US09750884

    申请日：2000-12-28

    申请人： John Maxwell Cohn ,  Alvar Antonio Dean ,  David James Hathaway ,  Patrick Edward Perry ,  Sebastian Theodore Ventrone

    发明人： John Maxwell Cohn ,  Alvar Antonio Dean ,  David James Hathaway ,  Patrick Edward Perry ,  Sebastian Theodore Ventrone

    IPC分类号： G05F304

    CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.

    摘要翻译： 一种用于提供片上电压分配和调节的系统和方法。 根据本发明的系统，IC芯片包括具有用于向IC芯片供电的源极电源轨的源极电压平面和用于从其供电的电力的源极接地导轨。 至少一个中间接地轨连接在源电源轨和源极接地轨之间，以将源电压平面分成多个中间电压平面。 中间接地导轨用作后续中间电压平面的电源轨，使得中间电压平面串联连接。

    DESIGN STRUCTURES INCLUDING CIRCUITS FOR NOISE REDUCTION IN DIGITAL SYSTEMS
    6.
    发明申请
    DESIGN STRUCTURES INCLUDING CIRCUITS FOR NOISE REDUCTION IN DIGITAL SYSTEMS 有权
    设计结构包括数字系统中减少噪声的电路

    公开(公告)号：US20090138676A1

    公开(公告)日：2009-05-28

    申请号：US11946096

    申请日：2007-11-28

    申请人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    发明人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： G06F1/06 ,  G06F1/08 ,  G06F9/3869

    摘要： A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 包括数字系统的设计结构。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

    Noise reduction in digital systems when the noise is caused by simultaneously clocking data registers
    7.
    发明授权
    Noise reduction in digital systems when the noise is caused by simultaneously clocking data registers 失效
    数字系统噪声降低时，噪声是由数据寄存器同步引起的

    公开(公告)号：US07463083B2

    公开(公告)日：2008-12-09

    申请号：US11937559

    申请日：2007-11-09

    申请人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    发明人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    IPC分类号： H03K5/00

    CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

    摘要： A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 数字系统 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

    Method and apparatus for providing bus arbitrations in a data processing system
    8.
    发明授权
    Method and apparatus for providing bus arbitrations in a data processing system 有权
    用于在数据处理系统中提供总线仲裁的方法和装置

    公开(公告)号：US06944698B2

    公开(公告)日：2005-09-13

    申请号：US10064379

    申请日：2002-07-08

    申请人： W. Riyon Harding ,  Thomas Michael Lepsic ,  Sebastian Theodore Ventrone

    发明人： W. Riyon Harding ,  Thomas Michael Lepsic ,  Sebastian Theodore Ventrone

    IPC分类号： G06F13/362

    CPC分类号： G06F13/362

    摘要： A method and apparatus for providing bus arbitrations in a multiprocessor system is disclosed. A computer system includes a common bus that is shared by multiple cores, such as processors. A history of bus requests for the common bus made by the cores is stored in a bus request history table. In response to bus request made by the cores, the common bus is arbitrated according to information stored in the bus request history table by an arbiter.

    摘要翻译： 公开了一种用于在多处理器系统中提供总线仲裁的方法和装置。 计算机系统包括由诸如处理器的多个核共享的公共总线。 总线请求历史记录表中存储有由核心产生的公共总线的总线请求的历史记录。 响应于核心的总线请求，公共总线根据仲裁器中存储在总线请求历史表中的信息进行仲裁。