公开(公告)号：US20090096392A1

公开(公告)日：2009-04-16

申请号：US12294001

申请日：2007-03-20

申请人： Manoj Chandran ,  Alma Anderson

发明人： Manoj Chandran ,  Alma Anderson

IPC分类号： H05B37/02

CPC分类号： H05B33/086 ,  H05B33/0818 ,  Y02B20/346

摘要： Methods and apparatus for implementing and operating pulse width modulation based LED dimmer controllers are described. A synchronization protocol is used to allow control information for the dimmer operations to be transferred to the PWM dimmer control clock domain from an external clock domain, such that visual artifacts are prevented when the control information is updated. Control information may be transferred to the LED dimmer controller via an I2C serial bus, and the synchronization protocol waits for an I2C STOP condition before updating control information across clock domain boundaries. The leading and trailing edges of an asserted group dimmer control signal are generated such that the active portion of the group dimmer control signal overlaps the active portion of individual LED pulse width modulated control signals. In this way, the pulse width modulation of the individual LED control signals is not cut off, or reduced in width by the group dimmer signal.

摘要翻译： 描述了实现和操作基于脉宽调制的LED调光控制器的方法和装置。 同步协议用于允许调光器操作的控制信息从外部时钟域传送到PWM调光控制时钟域，使得当更新控制信息时可防止视觉伪像。 控制信息可以通过I2C串行总线传输到LED调光控制器，并且在更新时钟域边界之间的控制信息之前，同步协议等待I2C STOP条件。 生成断言组调光控制信号的前沿和后沿，使得组调光控制信号的有效部分与各个LED脉冲宽度调制控制信号的有效部分重叠。 以这种方式，各个LED控制信号的脉冲宽度调制不被切断，或者通过组调光信号减小宽度。

公开(公告)号：US07990081B2

公开(公告)日：2011-08-02

申请号：US12294001

申请日：2007-03-20

申请人： Manoj Chandran ,  Alma Anderson

发明人： Manoj Chandran ,  Alma Anderson

IPC分类号： H05B37/00 ,  H05B39/00 ,  H05B41/00

CPC分类号： H05B33/086 ,  H05B33/0818 ,  Y02B20/346

摘要： Methods and apparatus for implementing and operating pulse width modulation based LED dimmer controllers are described. A synchronization protocol is used to allow control information for the dimmer operations to be transferred to the PWM dimmer control clock domain from an external clock domain, such that visual artifacts are prevented when the control information is updated. Control information may be transferred to the LED dimmer controller via an I2C serial bus, and the synchronization protocol waits for an I2C STOP condition before updating control information across clock domain boundaries. The leading and trailing edges of an asserted group dimmer control signal are generated such that the active portion of the group dimmer control signal overlaps the active portion of individual LED pulse width modulated control signals. In this way, the pulse width modulation of the individual LED control signals is not cut off, or reduced in width by the group dimmer signal.

摘要翻译： 描述了实现和操作基于脉宽调制的LED调光控制器的方法和装置。 同步协议用于允许调光器操作的控制信息从外部时钟域传送到PWM调光控制时钟域，使得当更新控制信息时可防止视觉伪像。 控制信息可以通过I2C串行总线传输到LED调光控制器，并且在更新时钟域边界之间的控制信息之前，同步协议等待I2C STOP条件。 生成断言组调光控制信号的前沿和后沿，使得组调光控制信号的有效部分与各个LED脉冲宽度调制控制信号的有效部分重叠。 以这种方式，各个LED控制信号的脉冲宽度调制不被切断，或者通过组调光信号减小宽度。

公开(公告)号：US20090121756A1

公开(公告)日：2009-05-14

申请号：US12294010

申请日：2007-03-20

申请人： Manoj Chandran ,  Jay Lory

发明人： Manoj Chandran ,  Jay Lory

IPC分类号： H03L7/00

CPC分类号： H04L7/0012 ,  G11C19/00

摘要： Methods and apparatus for implementing and operating one or more pseudo-synchronous registers with reduced power consumption, and reduced complexity for transferring data between clock domains. Various embodiments of the present invention replace conventional continuous clocking schemes with a strobe signal that is only generated when a data transfer operation with the one or more pseudo-synchronous registers is to take place. The strobe signal is generated so as to have a duration of one full cycle of the clock signal which defines the clock domain in which the at least one pseudo-synchronous register resides.

摘要翻译： 用于实现和操作具有降低的功耗的一个或多个伪同步寄存器的方法和装置，以及降低在时钟域之间传送数据的复杂性。 本发明的各种实施例用仅在要发生与一个或多个伪同步寄存器的数据传送操作时产生的选通信号来代替常规的连续计时方案。 产生选通信号以便具有定义至少一个伪同步寄存器所在的时钟域的时钟信号的一整个周期的持续时间。

公开(公告)号：US20100001786A1

公开(公告)日：2010-01-07

申请号：US12520009

申请日：2007-12-20

申请人： Anand Ramachandran ,  Manoj Chandran

发明人： Anand Ramachandran ,  Manoj Chandran

IPC分类号： H03K3/01

CPC分类号： G06F13/1689 ,  Y02D10/14

摘要： A method of accessing electronic memory is provided in electronic circuits where it is desired to lower power consumption and hence there is no active oscillator at the time when access to data within the electronic memory is required. The invention provides a method therefore for accessing the electronic memory from a controller, which generates its own clock signals from a data, communications bus electrically coupled to the controller. Advantageously the method allows for memory access to be continued in integrated circuits where a subset of circuits are powered down to reduce power consumption, and one of the subset of circuits is an oscillator.

摘要翻译： 在需要降低功耗的电子电路中提供了访问电子存储器的方法，因此在需要访问电子存储器内的数据时没有活动振荡器。 本发明提供了一种用于从控制器访问电子存储器的方法，控制器从控制器电连接的数据通信总线产生其自己的时钟信号。 有利地，该方法允许在集成电路中继续存储器访问，其中电路的子集被掉电以降低功耗，并且电路子集之一是振荡器。

公开(公告)号：US08185771B2

公开(公告)日：2012-05-22

申请号：US12520009

申请日：2007-12-20

申请人： Anand Ramachandran ,  Manoj Chandran

发明人： Anand Ramachandran ,  Manoj Chandran

IPC分类号： G06F1/00

CPC分类号： G06F13/1689 ,  Y02D10/14

摘要： A method of accessing electronic memory is provided in electronic circuits where it is desired to lower power consumption and hence there is no active oscillator at the time when access to data within the electronic memory is required. The invention provides a method therefore for accessing the electronic memory from a controller, which generates its own clock signals from a data, communications bus electrically coupled to the controller. Advantageously the method allows for memory access to be continued in integrated circuits where a subset of circuits are powered down to reduce power consumption, and one of the subset of circuits is an oscillator.

摘要翻译： 在需要降低功耗的电子电路中提供了访问电子存储器的方法，因此在需要访问电子存储器内的数据时没有活动振荡器。 本发明提供了一种用于从控制器访问电子存储器的方法，控制器从控制器电连接的数据通信总线产生其自己的时钟信号。 有利地，该方法允许在集成电路中继续存储器访问，其中电路的子集被掉电以降低功耗，并且电路子集之一是振荡器。

公开(公告)号：US06543018B1

公开(公告)日：2003-04-01

申请号：US09454244

申请日：1999-12-02

申请人： Swaroop Adusumilli ,  Manoj Chandran

发明人： Swaroop Adusumilli ,  Manoj Chandran

IPC分类号： G01R3128

CPC分类号： G01R31/318547

摘要： The present invention is a system and method that facilitates flexible restriction of output transmissions from chosen scan test cells and reduces adverse impacts on functional components from coincidental test vector values during scan test operations. The system and method of the present invention provides the capability of masking test vector values that coincidentally trigger certain undesirable events in functional components. In one embodiment, a system and method of the present invention masks test vector values shifted into scan test cells that are coupled to bus driver enabling signals. The system and method of the of the present invention also facilitates flexible selection of which scan test cell outputs are masked and permits a scan test cell to provide a scan test vector value to an associated functional component and prevent coincidental transmission of inappropriate test vector values.

摘要翻译： 本发明是一种系统和方法，其有助于灵活地限制来自所选择的扫描测试单元的输出传输，并且在扫描测试操作期间减少对巧合测试向量值对功能组件的不利影响。 本发明的系统和方法提供了屏蔽测试向量值的能力，其巧妙地触发功能组件中的某些不良事件。 在一个实施例中，本发明的系统和方法掩盖移入耦合到总线驱动使能信号的扫描测试单元的测试向量值。 本发明的系统和方法还有助于灵活地选择哪个扫描测试单元输出被屏蔽，并允许扫描测试单元向相关联的功能组件提供扫描测试向量值，并防止错误的测试矢量值的巧合传输。