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公开(公告)号：US5289281A
公开(公告)日：1994-02-22
申请号：US880304
申请日：1992-05-05
摘要： A system for recording one or more individual fields or frames of a color, high definition video signal. In a preferred embodiment, the system is capable of digitally recording as many as 32 frames of a color, high definition video signal per memory board, and as many as four memory boards may be installed in the system. The invention is capable of performing partial or full frame (or field) transfers at any selected rate less than or equal to the standard video rate. In a preferred embodiment, the system of the invention accepts HDTV signals in either digital or analog format, includes a post processing unit for simultaneously reconstructing stored HDTV signals in both digital and analog format, and a control unit which emulates a conventional video tape recorder (in the sense that it responds to conventional video tape recorder control signals) for controlling the system's frame memory. The invention includes a parallel computer interface which permits transfer of full or partial fields or frames (in non-real time) between the frame memory and an external computer (or image processing unit) via a conventional communication link. The control unit and an interface unit including the parallel computer interface are connected by a serial communications link, so that a host computer may control memory access through the interface unit.
摘要翻译： 一种用于记录彩色高分辨率视频信号的一个或多个单独场或帧的系统。 在优选实施例中，该系统能够对每个存储器板数字记录多达32帧的彩色高清晰度视频信号，并且可以在系统中安装多达四个存储器板。 本发明能够以小于或等于标准视频速率的任何选定的速率进行部分或全帧（或场）传送。 在优选实施例中，本发明的系统接收数字或模拟格式的HDTV信号，包括用于同时重建数字和模拟格式的存储的HDTV信号的后处理单元，以及模拟传统录像机的控制单元 在某种意义上说，它响应传统的录像机控制信号），用于控制系统的帧存储器。 本发明包括一个并行计算机接口，其允许经由传统通信链路在帧存储器和外部计算机（或图像处理单元）之间传输全部或部分字段或帧（非实时的）。 控制单元和包括并行计算机接口的接口单元通过串行通信链路连接，使得主计算机可以通过接口单元来控制存储器访问。
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2.发明授权
公开(公告)号：US4901150A
公开(公告)日：1990-02-13
申请号：US274820
申请日：1988-11-22
申请人： Marc Klingelhofer , Vinson R. Perry
发明人： Marc Klingelhofer , Vinson R. Perry
IPC分类号： H04N5/21
CPC分类号： H04N5/21
摘要： A method and system for separating a noise signal into frequency components, then automatically performing noise reduction on the individual frequency components, and then recombining the processed frequency components to generate an output noise signal. The noise reduction parameters for each frequency component may be independently set. The output noise signal generated during performance of the invention will typically be recombined with a signal (such as a television signal) from which the input noise signal for the invention was originally extracted. In a preferred embodiment, the input noise signal supplied to the system of the invention is generated by subtracting two adjacent frames of a television signal. In a preferred embodiment, the system of the invention includes: circuitry for implementing a Walsh-Hadamard transform to separate the input noise signal into a set of frequency components; a set of automatic gain controlled amplifiers for independently performing noise reduction on each frequency component; and a noise component collator for combining the processed frequency components to generate a "component controlled noise signal". Each automatic gain controlled amplifier is independently controlled in response to a feedback signal representing the noise characteristics of a different frequency component of the input noise signal. Preferably, the system of the invention also includes a gain controlled amplifier for transforming the component controlled noise signal into a gain controlled noise output signal.
摘要翻译： 一种用于将噪声信号分离成频率成分的方法和系统，然后对各个频率分量自动执行降噪，然后将经处理的频率分量重组以产生输出噪声信号。 可以独立地设置每个频率分量的降噪参数。 在本发明的执行期间产生的输出噪声信号通常将与最初提取本发明的输入噪声信号的信号（例如电视信号）重组。 在优选实施例中，通过减去电视信号的两个相邻帧来产生提供给本发明的系统的输入噪声信号。 在优选实施例中，本发明的系统包括：用于实现沃尔什 - 哈达玛变换以将输入噪声信号分离成一组频率分量的电路; 一组用于在每个频率分量上独立执行降噪的自动增益控制放大器; 以及用于组合经处理的频率分量以产生“分量控制的噪声信号”的噪声分量整理器。 响应于表示输入噪声信号的不同频率分量的噪声特性的反馈信号，每个自动增益控制放大器被独立地控制。 优选地，本发明的系统还包括用于将分量受控噪声信号变换成增益受控噪声输出信号的增益控制放大器。
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3.发明授权Digital video frame recorder with video display test pattern signal generator 失效数字视频录像机，带视频显示测试码信号发生器
公开(公告)号：US5055928A
公开(公告)日：1991-10-08
申请号：US507367
申请日：1990-04-10
申请人： Marc Klingelhofer
发明人： Marc Klingelhofer
CPC分类号： H04N17/06 , H04N17/045
摘要： A digital video frame recorder which includes an internal video display test pattern signal generator constructed substantially from already existing circuitry and hardware. A microprocessor and read only memor ("ROM") and/or random access memory ("RAM") used for performing preprogrammed self-diagnostic testing upon the digital video frame recorder are additionally programmed so that the user can selectively enable the internal video display test pattern signal generator. The internally generated video display test pattern signal data is stored within the frame memory in memory locations not normally used for storage of externally sourced video data. The internally generated video display test pattern signal data can be generated by sequentially reading out preprogrammed video display test pattern signal data directly from the ROM or RAM, or by having the microprocessor execute preprogrammed instructions stored in the ROM or RAM and thereby compute the video display test pattern signal data directly.
摘要翻译： 一种数字视频帧记录器，其包括基本上由现有的电路和硬件构成的内部视频显示测试图形信号发生器。 用于在数字视频帧记录器上执行预编程的自诊断测试的微处理器和只读存储器（“ROM”）和/或随机存取存储器（“RAM”）被附加地编程，使得用户可以选择性地启用内部视频显示 测试模式信号发生器。 内部生成的视频显示测试图形信号数据被存储在帧存储器中，而不是用于存储外部来源的视频数据的存储位置。 可以通过从ROM或RAM直接顺序读出预编程的视频显示测试图形信号数据，或者通过使微处理器执行存储在ROM或RAM中的预编程指令，从而计算出视频显示，从而产生内部生成的视频显示测试图形信号数据 直接测试模式信号数据。
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4.发明授权Control circuit for a buffer memory to transfer data between systems operating at different speeds 失效用于缓冲存储器的控制电路，用于在以不同速度运行的系统之间传输数据
公开(公告)号：US5884099A
公开(公告)日：1999-03-16
申请号：US655850
申请日：1996-05-31
申请人： Marc Klingelhofer
发明人： Marc Klingelhofer
CPC分类号： G06F5/10
摘要： The present invention relates to a simplified flag control circuitry for use in first in first out (FIFO) memory buffers. The special FIFO memory buffer transfers data between circuits running on different clocks. The present invention delays the initial output of data from the FIFO memory buffer until the memory buffer has received a threshold amount of data. After the threshold quantity of data has been received, the present invention allows output of data from the FIFO.
摘要翻译： 本发明涉及用于先进先出（FIFO）存储器缓冲器的简化标志控制电路。 专用FIFO存储器缓冲器在不同时钟运行的电路之间传输数据。 本发明延迟来自FIFO存储器缓冲器的数据的初始输出，直到存储器缓冲器已经接收到阈值量的数据。 在接收到阈值数量之后，本发明允许从FIFO输出数据。
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