Accelerated dual-display
    1.
    发明申请
    Accelerated dual-display 审中-公开
    加速双显示

    公开(公告)号:US20050134569A1

    公开(公告)日:2005-06-23

    申请号:US10746486

    申请日:2003-12-23

    摘要: An accelerated dual display enabling a user to dynamically decide which graphics subsystem will run which display on a handheld device. The dual display system has an application processor and an external chip. A crossbar located in the external chip connects the application processor to the external chip. Displays are connected to the crossbar.

    摘要翻译: 加速双显示,使用户能够动态地决定在手持设备上显示哪个图形子系统。 双显示系统具有应用处理器和外部芯片。 位于外部芯片的横杆将应用处理器连接到外部芯片。 显示器连接到交叉开关。

    Multiplexing digital video out on an accelerated graphics port interface
    2.
    发明授权
    Multiplexing digital video out on an accelerated graphics port interface 失效
    在加速图形端口接口上复用数字视频

    公开(公告)号:US06724389B1

    公开(公告)日:2004-04-20

    申请号:US09823107

    申请日:2001-03-30

    IPC分类号: G06F1314

    CPC分类号: G06F3/14

    摘要: The present invention is a method and apparatus to map first graphics pins into second graphics pins. A first plurality of data and command pins corresponding to data and command signals in a first graphics mode is mapped into a second plurality of data and command pins corresponding to data and command signals in a second graphics mode. The first and second graphics modes are supported by a first chipset. The second graphics mode is supported by a second chipset. A detector pin strappable to a logic level to indicate an external graphics card is used in the first graphics mode is mapped into a first pin corresponding to a first signal of the second graphics mode. The first signal is ignored by the second chipset during initialization.

    摘要翻译: 本发明是将第一图形引脚映射到第二图形引脚的方法和装置。 与第一图形模式中的数据和命令信号相对应的第一多个数据和命令引脚被映射到与第二图形模式中的数据和命令信号相对应的第二多个数据和命令引脚。 第一和第二图形模式由第一芯片组支持。 第二个图形模式由第二个芯片组支持。 在第一图形模式中使用被封装成逻辑电平以指示外部图形卡的检测器引脚被映射到对应于第二图形模式的第一信号的第一引脚。 第一个信号在初始化期间被第二个芯片组忽略。

    Low power display refresh
    3.
    发明授权
    Low power display refresh 有权
    低功耗显示刷新

    公开(公告)号:US07734943B2

    公开(公告)日:2010-06-08

    申请号:US10407758

    申请日:2003-04-03

    IPC分类号: G06F1/32

    摘要: An application processor coupled to a Static Random Access Memory (SRAM) interfaces with a graphics accelerator. A Dynamic Random Access Memory (DRAM) stores frame buffer data that may be transferred to a display through a switch located on the graphics accelerator in normal operation. In a power savings mode, the DRAM may be powered down and a copied frame buffer data stored in the SRAM may be transferred to the display through the switch.

    摘要翻译: 耦合到与图形加速器的静态随机存取存储器(SRAM)接口的应用处理器。 动态随机存取存储器(DRAM)存储可以在正常操作中通过位于图形加速器上的开关传送到显示器的帧缓冲器数据。 在省电模式中,DRAM可以被断电,并且存储在SRAM中的复制的帧缓冲器数据可以通过开关传送到显示器。