公开(公告)号：US20120112277A1

公开(公告)日：2012-05-10

申请号：US13284011

申请日：2011-10-28

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/265 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

摘要翻译： 一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。 下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。 一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。 一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

公开(公告)号：US09806190B2

公开(公告)日：2017-10-31

申请号：US13282305

申请日：2011-10-26

申请人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

发明人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/12 ,  H01L29/10 ,  H01L29/861 ,  H01L27/06

CPC分类号： H01L29/7824 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/7818 ,  H01L29/7835 ,  H01L29/861

摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

公开(公告)号：US08853029B2

公开(公告)日：2014-10-07

申请号：US13188162

申请日：2011-07-21

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734

摘要： An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.

摘要翻译： 电子器件具有形成在半导体层中的多个沟槽。 垂直漂移区域位于沟槽之间和相邻的沟槽之间。 电极位于每个沟槽内，电极具有栅电极部分和场板部分。 在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。

公开(公告)号：US20120104497A1

公开(公告)日：2012-05-03

申请号：US13282305

申请日：2011-10-26

申请人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

发明人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7824 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/7818 ,  H01L29/7835 ,  H01L29/861

摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

摘要翻译： SOI衬底上的集成电路，其包含在漏极（n沟道）或体区（p沟道）中具有穿通衬底二极管的扩展漏极MOS晶体管，使得漏极或体区域通过pn耦合到处理晶片 交界处 在SOI衬底上的集成电路，其包含通过pn结耦合到处理晶片的漏极（n沟道）或体区（p沟道）中的贯穿衬底二极管的延伸漏极MOS晶体管，其与 排水或身体区域。 在包含漏极（n沟道）或体区（p沟道）中的贯通衬底二极管的延伸漏极MOS晶体管的SOI衬底上形成集成电路的工艺。

公开(公告)号：US08872273B2

公开(公告)日：2014-10-28

申请号：US13567340

申请日：2012-08-06

申请人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

发明人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

IPC分类号： H01L27/11 ,  H01L27/06 ,  H01L49/02

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

摘要翻译： 一种集成电路，其包含栅极控制分压器，该栅极控制分压器具有与场效应晶体管上的上电阻串联的晶体管开关，与下电阻串联。 电阻器漂移层设置在上电阻器下方，并且晶体管开关包括与电阻器漂移层相邻的开关漂移层，由防止漂移层之间的击穿的区域分开。 开关漂移层为晶体管开关提供了扩展的漏极或集电极。 分压器的感测端子耦合到晶体管的源极或发射极节点和下电阻器。 输入端子耦合到上电阻器和电阻漂移层。 形成包含栅极控制分压器的集成电路的工艺。

公开(公告)号：US20100264486A1

公开(公告)日：2010-10-21

申请号：US12426717

申请日：2009-04-20

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734

摘要： An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region.

摘要翻译： 电子器件具有形成在半导体层中的多个沟槽。 垂直漂移区域位于沟槽之间和相邻的沟槽之间。 电极位于每个沟槽内，电极具有栅电极部分和场板部分。 梯度场板电介质位于场板部分和垂直漂移区之间。

公开(公告)号：US20130032922A1

公开(公告)日：2013-02-07

申请号：US13567456

申请日：2012-08-06

申请人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

发明人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

IPC分类号： H01L29/06 ,  H01L21/761

CPC分类号： H01L21/761 ,  H01L21/266

摘要： An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

摘要翻译： 一种集成电路，包括分压器，该分压器具有围绕中心开口的场氧化物上的非硅栅极材料的上电阻器，以及位于上电阻器下的漂移层的输入端子，所述输入端子与所述上电阻器的输入节点相邻， 场氧化物并通过中心开口耦合到漂移层，感测端子耦合到与输入节点相反的上电阻上的感测节点，具有耦合到感测端子的检测节点和参考节点的下电阻器，以及 参考终端耦合到参考节点。 形成包含分压器的集成电路的工艺。

公开(公告)号：US20130032863A1

公开(公告)日：2013-02-07

申请号：US13567340

申请日：2012-08-06

申请人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

发明人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

IPC分类号： H01L27/07 ,  H01L21/20

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

摘要翻译： 一种集成电路，其包含栅极控制分压器，该栅极控制分压器具有与场效应晶体管上的上电阻串联的晶体管开关，与下电阻串联。 电阻器漂移层设置在上电阻器下方，并且晶体管开关包括与电阻器漂移层相邻的开关漂移层，由防止漂移层之间的击穿的区域分开。 开关漂移层为晶体管开关提供了扩展的漏极或集电极。 分压器的感测端子耦合到晶体管的源极或发射极节点和下电阻器。 输入端子耦合到上电阻器和电阻漂移层。 形成包含栅极控制分压器的集成电路的工艺。

公开(公告)号：US08878330B2

公开(公告)日：2014-11-04

申请号：US13567456

申请日：2012-08-06

申请人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

发明人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

IPC分类号： H01L29/02 ,  H01L21/761 ,  H01L21/266

CPC分类号： H01L21/761 ,  H01L21/266

摘要： An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

摘要翻译： 一种集成电路，包括分压器，该分压器具有围绕中心开口的场氧化物上的非硅栅极材料的上电阻器，以及位于上电阻器下的漂移层的输入端子，所述输入端子与所述上电阻器的输入节点相邻， 场氧化物并通过中心开口耦合到漂移层，感测端子耦合到与输入节点相反的上电阻上的感测节点，具有耦合到感测端子的检测节点和参考节点的下电阻器，以及 参考终端耦合到参考节点。 形成包含分压器的集成电路的工艺。

公开(公告)号：US08476127B2

公开(公告)日：2013-07-02

申请号：US13284011

申请日：2011-10-28

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

IPC分类号： H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/265 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

摘要翻译： 一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。 下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。 一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。 一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。