公开(公告)号：US08424071B2

公开(公告)日：2013-04-16

申请号：US12621570

申请日：2009-11-19

申请人： Mariette Awad ,  Deanna C. Lim ,  Pascal A. Nsame ,  Daneyand J. Singley ,  Sebastian T. Ventrone

发明人： Mariette Awad ,  Deanna C. Lim ,  Pascal A. Nsame ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F7/04

CPC分类号： G06F21/55 ,  G06F21/31

摘要： In one embodiment, the invention is a method and apparatus for secure and reliable computing. One embodiment of an end-to-end security system for protecting a computing system includes a processor interface coupled to at least one of an application processor and an accelerator of the computing system, for receiving requests from the at least one of the application processor and the accelerator, a security processor integrating at least one embedded storage unit and connected to the processor interface with a tightly coupled memory unit for performing at least one of: authenticating, managing, monitoring, and processing the requests, and a data interface for communicating with a display, a network, and at least one embedded storage unit for securely holding at least one of data and programs used by the at least one of the application processor and the accelerator.

公开(公告)号：US20090251474A1

公开(公告)日：2009-10-08

申请号：US12099183

申请日：2008-04-08

申请人： Deanna J. Chou ,  Jesse E. Craig ,  Pascal A. Nsame ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

发明人： Deanna J. Chou ,  Jesse E. Craig ,  Pascal A. Nsame ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06T1/00

CPC分类号： G06T15/005 ,  G06T2200/16

摘要： A virtual computing and display system and method. The system includes a plurality of microprocessor-based devices which run software applications, and each microprocessor-based device generates at least one graphic processing unit command stream including a packet of graphic commands. The system further includes at least one communication network which directly receives the graphics processing unit command stream from each of the microprocessor-based devices and transfers each of the generated graphics processing unit command streams via a respective active channel, at least one multi-core adaptive display server which receives and processes the graphics processing unit command streams, and at least one display which receives the packets via the at least one active channel per user session and displays at least one image. The at least one active channel connects a respective microprocessor-based device, the communication network, the at least one multi-core adaptive display server and the at least one display.

摘要翻译： 虚拟计算和显示系统及方法。 该系统包括运行软件应用的多个基于微处理器的设备，并且每个基于微处理器的设备生成包括图形命令的分组的至少一个图形处理单元命令流。 该系统还包括至少一个通信网络，其直接从每个基于微处理器的设备接收图形处理单元命令流，并经由相应的活动信道传送每个生成的图形处理单元命令流，至少一个多核自适应 显示服务器，其接收和处理图形处理单元命令流，以及至少一个显示器，其通过每个用户会话的至少一个活动频道接收分组并显示至少一个图像。 所述至少一个活动通道连接相应的基于微处理器的设备，通信网络，至少一个多核自适应显示服务器和至少一个显示器。

公开(公告)号：US07865862B2

公开(公告)日：2011-01-04

申请号：US11937106

申请日：2007-11-08

申请人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

发明人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F9/3836 ,  G06F9/3885

摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括用于动态选择编译指令进行执行的装置，该装置包括用于接收用于在第一执行单元上执行的静态指令的输入，以及在第二执行单元上接收用于执行的动态指令 执行单位 以及指令选择元件，其适于基于所述执行单元的当前状态来评估所述静态指令和动态指令的吞吐量性能，并分别在所述第一执行单元或所述第二执行单元上的运行时选择所述静态指令或用于执行的所述动态指令 ，基于指令的吞吐量性能。

公开(公告)号：US20090031111A1

公开(公告)日：2009-01-29

申请号：US11828705

申请日：2007-07-26

申请人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

发明人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3897 ,  G06F15/7867

摘要： A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

摘要翻译： 一种方法，装置和计算机程序产品动态地选择编译指令进行执行。 接收用于在第一执行上执行的静态指令和用于在第二执行单元上执行的动态指令。 基于执行单元的当前状态来评估静态指令和动态指令的吞吐量性能。 基于指令的吞吐量性能，静态指令或动态指令分别被选择用于在运行时在第一执行单元或第二执行单元上执行。

公开(公告)号：US07761690B2

公开(公告)日：2010-07-20

申请号：US11828705

申请日：2007-07-26

申请人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

发明人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F9/48

CPC分类号： G06F9/3836 ,  G06F9/3897 ,  G06F15/7867

摘要： A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

摘要翻译： 一种方法，装置和计算机程序产品动态地选择编译指令进行执行。 接收用于在第一执行上执行的静态指令和用于在第二执行单元上执行的动态指令。 基于执行单元的当前状态来评估静态指令和动态指令的吞吐量性能。 基于指令的吞吐量性能，静态指令或动态指令分别被选择用于在运行时在第一执行单元或第二执行单元上执行。

公开(公告)号：US20090125704A1

公开(公告)日：2009-05-14

申请号：US11937106

申请日：2007-11-08

申请人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

发明人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F9/30 ,  G06F9/46

CPC分类号： G06F9/3836 ,  G06F9/3885

摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括用于动态选择编译指令进行执行的装置，该装置包括用于接收用于在第一执行单元上执行的静态指令的输入，以及在第二执行单元上接收用于执行的动态指令 执行单位 以及指令选择元件，其适于基于所述执行单元的当前状态来评估所述静态指令和动态指令的吞吐量性能，并分别在所述第一执行单元或所述第二执行单元上的运行时选择所述静态指令或用于执行的所述动态指令 ，基于指令的吞吐量性能。

公开(公告)号：US20080263489A1

公开(公告)日：2008-10-23

申请号：US11738535

申请日：2007-04-23

申请人： Miles G. Canada ,  Ian R. Govett ,  John Sargis ,  Daryl M. Seitzer ,  Daneyand J. Singley ,  Abhijeet R. Tanpure ,  Manikandan Viswanath

发明人： Miles G. Canada ,  Ian R. Govett ,  John Sargis ,  Daryl M. Seitzer ,  Daneyand J. Singley ,  Abhijeet R. Tanpure ,  Manikandan Viswanath

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G01R31/318364

摘要： A method of testing critical paths in integrated circuits begins by simulating at least one operation of an integrated circuit chip design to produce chip timing data. Next, critical paths of the integrated circuit chip design are identified based on the chip timing data. The method applies functional test signals to simulations of the critical paths and monitors the number of times each of the functional test signals propagate from the beginning to the end of each of the critical paths. This allows the method to identify stress producing test signals as those that propagate along the critical paths more than other test signals. These stress producing test signals are applied to integrated circuit chip hardware manufactured according to the integrated circuit chip design to stress test the hardware.

摘要翻译： 在集成电路中测试关键路径的方法开始于模拟集成电路芯片设计的至少一个操作以产生芯片定时数据。 接下来，基于芯片定时数据来识别集成电路芯片设计的关键路径。 该方法将功能测试信号应用于关键路径的仿真，并监视每个功能测试信号从每个关键路径的开始到结束传播的次数。 这允许该方法识别产生应力的测试信号，作为沿着关键路径比其它测试信号传播的信号。 这些应力产生测试信号被应用于根据集成电路芯片设计制造的集成电路芯片硬件来对硬件进行测试。

公开(公告)号：US08595468B2

公开(公告)日：2013-11-26

申请号：US12640112

申请日：2009-12-17

申请人： Shawn M. Luke ,  John Sargis, Jr. ,  Daneyand J. Singley

发明人： Shawn M. Luke ,  John Sargis, Jr. ,  Daneyand J. Singley

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3885 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3828 ,  G06F9/3851

摘要： A multi-core processor system supporting simultaneous thread sharing across execution resources of multiple processor cores is provided. The multi-core processor system includes a first processor core with a first instruction queue and dispatch logic in communication with a first execution resource of the first processor core. The multi-core processor system also includes a second processor core with a second instruction queue and dispatch logic in communication with a second execution resource of the second processor core. A high-speed execution resource bus couples the first and second processor cores. The first instruction queue and dispatch logic is configured to issue a first instruction of a thread to the first execution resource and issue a second instruction of the thread over the high-speed execution resource bus to the second execution resource for simultaneous execution of the first and second instruction of the thread on the first and second processor cores.

摘要翻译： 提供了支持跨多个处理器核心的执行资源同时进行线程共享的多核处理器系统。 多核处理器系统包括具有第一指令队列的第一处理器核心和与第一处理器核心的第一执行资源通信的调度逻辑。 多核处理器系统还包括具有第二指令队列的第二处理器核心和与第二处理器核心的第二执行资源通信的调度逻辑。 高速执行资源总线耦合第一和第二处理器核心。 第一指令队列和调度逻辑被配置为向第一执行资源发出线程的第一指令，并且通过高速执行资源总线向第二执行资源发出线程的第二指令，以同时执行第一和 线程在第一和第二处理器核心上的第二条指令。

公开(公告)号：US20110153987A1

公开(公告)日：2011-06-23

申请号：US12640112

申请日：2009-12-17

申请人： Shawn M. Luke ,  John Sargis, JR. ,  Daneyand J. Singley

发明人： Shawn M. Luke ,  John Sargis, JR. ,  Daneyand J. Singley

IPC分类号： G06F9/30 ,  G06F9/46

CPC分类号： G06F9/3885 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3828 ,  G06F9/3851

摘要： A multi-core processor system supporting simultaneous thread sharing across execution resources of multiple processor cores is provided. The multi-core processor system includes a first processor core with a first instruction queue and dispatch logic in communication with a first execution resource of the first processor core. The multi-core processor system also includes a second processor core with a second instruction queue and dispatch logic in communication with a second execution resource of the second processor core. A high-speed execution resource bus couples the first and second processor cores. The first instruction queue and dispatch logic is configured to issue a first instruction of a thread to the first execution resource and issue a second instruction of the thread over the high-speed execution resource bus to the second execution resource for simultaneous execution of the first and second instruction of the thread on the first and second processor cores.

摘要翻译： 提供了支持跨多个处理器核心的执行资源同时进行线程共享的多核处理器系统。 多核处理器系统包括具有第一指令队列的第一处理器核心和与第一处理器核心的第一执行资源通信的调度逻辑。 多核处理器系统还包括具有第二指令队列的第二处理器核心和与第二处理器核心的第二执行资源通信的调度逻辑。 高速执行资源总线耦合第一和第二处理器核心。 第一指令队列和调度逻辑被配置为向第一执行资源发出线程的第一指令，并且通过高速执行资源总线向第二执行资源发出线程的第二指令，以同时执行第一和 线程在第一和第二处理器核心上的第二条指令。