公开(公告)号：US20080263489A1

公开(公告)日：2008-10-23

申请号：US11738535

申请日：2007-04-23

申请人： Miles G. Canada ,  Ian R. Govett ,  John Sargis ,  Daryl M. Seitzer ,  Daneyand J. Singley ,  Abhijeet R. Tanpure ,  Manikandan Viswanath

发明人： Miles G. Canada ,  Ian R. Govett ,  John Sargis ,  Daryl M. Seitzer ,  Daneyand J. Singley ,  Abhijeet R. Tanpure ,  Manikandan Viswanath

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G01R31/318364

摘要： A method of testing critical paths in integrated circuits begins by simulating at least one operation of an integrated circuit chip design to produce chip timing data. Next, critical paths of the integrated circuit chip design are identified based on the chip timing data. The method applies functional test signals to simulations of the critical paths and monitors the number of times each of the functional test signals propagate from the beginning to the end of each of the critical paths. This allows the method to identify stress producing test signals as those that propagate along the critical paths more than other test signals. These stress producing test signals are applied to integrated circuit chip hardware manufactured according to the integrated circuit chip design to stress test the hardware.

摘要翻译： 在集成电路中测试关键路径的方法开始于模拟集成电路芯片设计的至少一个操作以产生芯片定时数据。 接下来，基于芯片定时数据来识别集成电路芯片设计的关键路径。 该方法将功能测试信号应用于关键路径的仿真，并监视每个功能测试信号从每个关键路径的开始到结束传播的次数。 这允许该方法识别产生应力的测试信号，作为沿着关键路径比其它测试信号传播的信号。 这些应力产生测试信号被应用于根据集成电路芯片设计制造的集成电路芯片硬件来对硬件进行测试。

公开(公告)号：US5634026A

公开(公告)日：1997-05-27

申请号：US440033

申请日：1995-05-12

申请人： Jay G. Heaslip ,  Miles G. Canada

发明人： Jay G. Heaslip ,  Miles G. Canada

IPC分类号： G06F9/38 ,  G06F9/28

CPC分类号： G06F9/384 ,  G06F9/3824 ,  G06F9/3885

摘要： In a method and apparatus for result forwarding, a source operand compare circuit for a reservation station for a superscalar processor having a plurality of execution units, includes a source identifier for identifying an execution unit that will produce a needed result. The source identifier is included with a rename tag associated with a respective source operand. A multiplexor controlled by the source identifier directs the result of an execution unit to a comparator. The comparator compares the rename tag with a specific reservation station identity. As a result of this comparison, the needed data result is supplied to the respective source operand.

摘要翻译： 在用于结果转发的方法和装置中，用于具有多个执行单元的超标量处理器的预留站的源操作数比较电路包括用于识别将产生所需结果的执行单元的源标识符。 源标识符包含在与相应的源操作数相关联的重命名标签中。 由源标识符控制的复用器将执行单元的结果引导到比较器。 比较器将重命名标签与特定的保留站标识进行比较。 作为该比较的结果，将所需的数据结果提供给相应的源操作数。

公开(公告)号：US5404049A

公开(公告)日：1995-04-04

申请号：US146253

申请日：1993-11-02

申请人： Miles G. Canada ,  Michael Nicewicz ,  John R. Rawlins ,  Carlos G. Rivadeneira

发明人： Miles G. Canada ,  Michael Nicewicz ,  John R. Rawlins ,  Carlos G. Rivadeneira

IPC分类号： H01H85/46 ,  G11C17/18 ,  H02H7/20

CPC分类号： G11C17/18

摘要： A chip can be provide with circuits to electrically read, blow and latch fuses. The circuit allows use of existing I/O pads used for other functions on a chip to drastically reduce the number of I/O required to blow fuses. The circuits also share critical high current carrying lines with no impact on fuse functionality and device reliability. By offering of complex fuse operations such as electrical override, even after they had been blown, essential for product screening and product diagnostics. The circuit provides a fuse blow circuit fed by a fuse sense circuit and fuse latch circuit. Stored addresses in an address buffer addresses the fuses with two sets of inputs: one providing electrical override and/or fuse blow information; and the second one, normal fuse status. Fuse integrity before and after blow is maximized with a dual voltage source drive and low current sensing.

摘要翻译： 一个芯片可以提供电路读取，打击和锁定保险丝。 该电路允许使用用于芯片上其他功能的现有I / O焊盘来大大减少熔断熔丝所需的I / O数量。 这些电路还共享关键的大电流承载线路，对熔断器功能和器件可靠性没有影响。 通过提供复杂的保险丝操作，例如电气超驰，甚至在吹制之后，对产品筛选和产品诊断至关重要。 该电路提供由熔丝检测电路和熔丝锁存电路馈送的保险丝熔断电路。 地址缓冲器中的存储地址用两组输入来对熔断器进行寻址：一个提供电气覆盖和/或保险丝熔断信息; 第二个，正常保险丝状态。 使用双电压源驱动和低电流检测来最大限度地提高吹入前后的保险丝完整性。

公开(公告)号：US07106110B2

公开(公告)日：2006-09-12

申请号：US10710681

申请日：2004-07-28

申请人： Miles G. Canada ,  Erwin B. Cohen ,  Jay G. Heaslip ,  Cedric Lichtenau ,  Thomas Pflueger ,  Mathew I. Ringler

发明人： Miles G. Canada ,  Erwin B. Cohen ,  Jay G. Heaslip ,  Cedric Lichtenau ,  Thomas Pflueger ,  Mathew I. Ringler

IPC分类号： H03B19/00

CPC分类号： G06F1/08 ,  G06F1/324 ,  Y02D10/126

摘要： A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.

摘要翻译： 一种将集成电路装置的时钟频率从第一频率转换到第二频率的系统和方法，包括根据抖动模式在第一频率和第二频率之间交替，交替发生预定数量的周期; 并且在预定次数的周期之后将时钟频率设置为第二频率。

公开(公告)号：US07042776B2

公开(公告)日：2006-05-09

申请号：US10708236

申请日：2004-02-18

申请人： Miles G. Canada ,  Stephen F. Geissler ,  Robert M. Houle ,  Dongho Lee ,  Vinod Ramadurai ,  Mathew I. Ringler ,  Gerard M. Salem ,  Timothy J. Vonreyn

发明人： Miles G. Canada ,  Stephen F. Geissler ,  Robert M. Houle ,  Dongho Lee ,  Vinod Ramadurai ,  Mathew I. Ringler ,  Gerard M. Salem ,  Timothy J. Vonreyn

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/1045 ,  G11C2207/065 ,  G11C2207/2254

摘要： A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.

摘要翻译： 一种用于调整自定时存储器阵列的读取余量的方法和电路。 该电子电路包括：存储单元阵列，包括适于设置存储单元阵列的基本读时间延迟的读出放大器自定时解码电路; 以及耦合到所述存储单元阵列的读延迟调整电路，所述读延迟调整电路适于基于所述存储单元阵列的工作频率来调整所述存储器阵列的基本读时间延迟。