公开(公告)号：US07647435B2

公开(公告)日：2010-01-12

申请号：US11761154

申请日：2007-06-11

申请人： Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

发明人： Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F13/36

摘要： A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.

摘要翻译： 用于数字设备的通信总线包括基于信用的流量控制机制，其中发送组件保持其信用的本地记录。 通过脉冲单位信用回报线将积分返还给发送方。 单独的机制提供来自接收器的可用信用的计数，单独的机制不一定是当前的。 将本地记录与预定时间间隔内的单独机制的信用计数进行比较，两个值在表示可能的信用差异的间隔期间的任何时间失败。 确认信用差异，最好是通过暂停一段长时间的公共汽车活动来解决传播信用额度变化的任何延误，并重新比较价值。 优选地，总线在集成电路芯片的内部部件之间进行通信。

公开(公告)号：US07249207B2

公开(公告)日：2007-07-24

申请号：US11047522

申请日：2005-01-31

申请人： Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

发明人： Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

IPC分类号： G06F13/12

CPC分类号： G06F13/4022

摘要： An integrated circuit chip includes multiple functional components and a central interconnect (CI) module. Each functional component communicates with the CI module via a respective internal bus sharing a common architecture which does not dictate any particular data alignment. The chip architecture defines an alignment mechanism within the CI module, which performs any required alignment of transmitted data. Alignment mechanism design parameters can be varied to accommodate different alignment domains of different functional components. Preferably, the common bus architecture supports multiple internal bus widths, the CI module performing any required bus width conversion. Preferably, for certain transactions not containing a data address, correct alignment is obtained by placing restrictions on transaction size and boundaries, and duplicating certain data on different alignment boundaries. The use of a common bus protocol and CI module having alignment capability streamlines the design process and reduces the overhead of alignment conversion.

摘要翻译： 集成电路芯片包括多个功能组件和中央互连（CI）模块。 每个功能组件通过共享具有不规定任何特定数据对准的公共架构的相应内部总线与CI模块通信。 芯片架构定义了CI模块内的对准机制，其执行传输数据的任何所需的对准。 对准机构设计参数可以变化以适应不同功能组件的不同对准域。 优选地，公共总线架构支持多个内部总线宽度，CI模块执行任何所需的总线宽度转换。 优选地，对于不包含数据地址的某些事务，通过对事务大小和边界进行限制并且在不同的对准边界上复制某些数据来获得正确的对准。 使用具有对准能力的公共总线协议和CI模块简化了设计过程并减少了对准转换的开销。

公开(公告)号：US07136954B2

公开(公告)日：2006-11-14

申请号：US11047547

申请日：2005-01-31

申请人： Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

发明人： Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

IPC分类号： G06F13/00

CPC分类号： G06F13/36

摘要： A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.

摘要翻译： 用于数字设备的通信总线包括基于信用的流量控制机制，其中发送组件保持其信用的本地记录。 通过脉冲单位信用回报线将积分返还给发件人。 单独的机制提供来自接收器的可用信用的计数，单独的机制不一定是当前的。 将本地记录与预先确定的时间间隔内的单独机制的信用计数进行比较，两个值在表示可能的信用差异的间隔期间的任何时间失败。 确认信用差异，最好是通过暂停一段长时间的公共汽车活动来解决传播信用额度变化的任何延误，并重新比较价值。 优选地，总线在集成电路芯片的内部部件之间进行通信。

公开(公告)号：US07882278B2

公开(公告)日：2011-02-01

申请号：US12362585

申请日：2009-01-30

申请人： Sundeep Chadha ,  Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

发明人： Sundeep Chadha ,  Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

IPC分类号： G06F13/42

CPC分类号： G06F13/4059

摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

摘要翻译： 用于数据总线通信的控制机制采用分配总线事务的通道，每个通道具有独立的流量控制。 控制机制强制通道之间的排序算法，由此至少一些交易可以通过其他交易。 通道属性可编程以改变排序条件。 优选地，每个信道被分配其自己的可编程缓冲区。 控制机制为每个通道独立地确定缓冲区空间是否可用，并相应地为每个通道独立地执行流量控制。 流量控制优选地是基于信用的，表示缓冲区空间的信用或接收器接收数据的一些其他容量。 优选地，流量控制机构包括控制集成电路芯片的内部通信的中央互连模块。

公开(公告)号：US20090138629A1

公开(公告)日：2009-05-28

申请号：US12362585

申请日：2009-01-30

申请人： Sundeep Chadha ,  Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

发明人： Sundeep Chadha ,  Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

IPC分类号： G06F13/42

CPC分类号： G06F13/4059

摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

摘要翻译： 用于数据总线通信的控制机制采用分配总线事务的通道，每个通道具有独立的流量控制。 控制机制强制通道之间的排序算法，由此至少一些交易可以通过其他交易。 通道属性可编程以改变排序条件。 优选地，每个信道被分配其自己的可编程缓冲区。 控制机制为每个通道独立地确定缓冲区空间是否可用，并相应地为每个通道独立地执行流量控制。 流量控制优选地是基于信用的，表示缓冲区空间的信用或接收器接收数据的一些其他容量。 优选地，流量控制机构包括控制集成电路芯片的内部通信的中央互连模块。

公开(公告)号：US07493426B2

公开(公告)日：2009-02-17

申请号：US11047548

申请日：2005-01-31

申请人： Sundeep Chadha ,  Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

发明人： Sundeep Chadha ,  Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F11/00 ,  G01R31/08 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26

CPC分类号： G06F13/4059

摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

摘要翻译： 用于数据总线通信的控制机制采用分配总线事务的通道，每个通道具有独立的流量控制。 控制机制强制通道之间的排序算法，由此至少一些交易可以通过其他交易。 通道属性可编程以改变排序条件。 优选地，每个信道被分配其自己的可编程缓冲区。 控制机制为每个通道独立地确定缓冲区空间是否可用，并相应地为每个通道独立地执行流量控制。 流量控制优选地是基于信用的，表示缓冲区空间的信用或接收器接收数据的一些其他容量。 优选地，流量控制机构包括控制集成电路芯片的内部通信的中央互连模块。

公开(公告)号：US07277974B2

公开(公告)日：2007-10-02

申请号：US11553500

申请日：2006-10-27

申请人： Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

发明人： Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

IPC分类号： G06F13/00

CPC分类号： G06F13/36

摘要： A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.

摘要翻译： 用于数字设备的通信总线包括基于信用的流量控制机制，其中发送组件保持其信用的本地记录。 通过脉冲单位信用回报线将积分返还给发件人。 单独的机制提供来自接收器的可用信用的计数，单独的机制不一定是当前的。 将本地记录与预定时间间隔内的单独机制的信用计数进行比较，两个值在表示可能的信用差异的间隔期间的任何时间失败。 确认信用差异，最好是通过暂停一段长时间的公共汽车活动来解决传播信用额度变化的任何延误，并重新比较价值。 优选地，总线在集成电路芯片的内部部件之间进行通信。

公开(公告)号：US6105126A

公开(公告)日：2000-08-15

申请号：US70359

申请日：1998-04-30

申请人： Mark Anthony Check ,  Ronald M. Smith, Sr. ,  John Stephen Liptay ,  Eric Mark Schwarz ,  Timothy John Slegel ,  Charles Franklin Webb

发明人： Mark Anthony Check ,  Ronald M. Smith, Sr. ,  John Stephen Liptay ,  Eric Mark Schwarz ,  Timothy John Slegel ,  Charles Franklin Webb

IPC分类号： G06F9/355 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/34

CPC分类号： G06F9/355 ,  G06F9/30185

摘要： A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular instruction and the base (B) and index (X) register values are read for use in address generation. RXE Instructions are of the RX-type but extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine the exact format from the first 8 bits of the operation code alone. ESA/390 instructions SS, RR; RX; S; RRE; RI; and the new RXE instructions have a format which can be used for fixed point processing as well as floating point processing where instructions of the RXE format have their R1, X2, B2, and D2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.

摘要翻译： 计算机处理器浮点处理器六循环流水线系统，其中指令文本在第一周期之前获取并且在第一周期期间被解码用于所提取的特定指令，并且基准（B）和索引（X）寄存器值被读取用于地址 代。 RXE指令是RX型，但通过将操作码的扩展置于指令格式的前四个字节之外进行扩展，并以这样的方式分配操作码，使得机器可以从前8位确定确切的格式 的操作代码。 ESA / 390指令SS，RR; RX; S; RRE; RI; 并且新的RXE指令具有可用于固定点处理以及浮点处理的格式，其中RXE格式的指令在所述指令寄存器中的相同位置具有其R1，X2，B2和D2字段，如 RX格式，使处理器能够从操作代码的前8位确定正在解码的指令是RXE格式指令和RXE格式指令的寄存器索引扩展，之后它将正确信息锁定到所述XBD加法器 。 在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所取出的指令 结果放在第六个周期。

公开(公告)号：US5694587A

公开(公告)日：1997-12-02

申请号：US414154

申请日：1995-03-31

申请人： Charles Franklin Webb ,  Mark Steven Farrell ,  Mark Anthony Check ,  John Stephen Liptay

发明人： Charles Franklin Webb ,  Mark Steven Farrell ,  Mark Anthony Check ,  John Stephen Liptay

IPC分类号： G06F9/30 ,  G06F9/305 ,  G06F9/318 ,  G06F9/38 ,  G06F11/07

CPC分类号： G06F9/3865 ,  G06F11/0721 ,  G06F11/0751 ,  G06F9/30029 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30189

摘要： A pipelined computer processor in a milli-mode architected state tests the validity of a program status word with a mask stored in a millicode general register. The mask indicates bits in the program status word which are to be zeros if the word is valid. A logical AND operation is performed between correspondingly positioned bits in the word and bits in the mask and in addition the status of at least one other bit in the word is checked, a bit other than a correspondingly positioned bit.

摘要翻译： 在毫模式架构状态下的流水线计算机处理器使用存储在毫通通用寄存器中的掩码测试程序状态字的有效性。 掩码表示程序状态字中的位，如果该字有效，则它们将为零。 在字中的相应位置的位和掩码中的位之间执行逻辑“与”运算，另外检查字中的至少一个其他位的状态，除了对应定位的位之外的位。

公开(公告)号：US6138215A

公开(公告)日：2000-10-24

申请号：US70575

申请日：1998-04-30

申请人： Mark Anthony Check ,  Jane Helen Bartik

发明人： Mark Anthony Check ,  Jane Helen Bartik

IPC分类号： G06F12/10

CPC分类号： G06F12/1054 ,  G06F12/0888

摘要： A computer processor that uses an AAHT to provide a guess at the real (absolute) address bits used to access the cache and directories that is more accurate in a high-frequency design which prevents any sort of full or large partial adds of ranges of base, index, or displacement has two index values generated and two AAHT arrays, one each for instruction and operand logical requests. It handles cases in which the data is not directly from the GPR array. For designs that aim at improving performance data for some operations that update GPR's may be used for address generation prior to the execution and write to the GPR array, these include data bypass for Load Address (LA) and Load (L). The system handles instruction fetches, relative branches, other special instruction address instruction fetch requests, and those started as a result of a branch history table (BHT) predicted instruction fetch. A method for AAHT synonym resolution improves the accuracy of the index value for an Absolute Address History Table buffer.

摘要翻译： 使用AAHT的计算机处理器提供用于访问高速缓存的实际（绝对）地址位和在高频设计中更准确的目录的猜测，其防止基站范围的任何类型的全部或大部分增加 ，索引或位移具有两个生成的索引值和两个AAHT数组，一个用于指令和操作数逻辑请求。 它处理数据不直接来自GPR数组的情况。 对于旨在改进性能数据的设计，更新GPR可能会在执行和写入GPR阵列之前产生地址，这些操作包括负载地址（LA）和负载（L）的数据旁路。 系统处理指令提取，相对分支，其他特殊指令地址指令取出请求以及作为分支历史表（BHT）预测指令获取结果启动的指令。 AAHT同义词分辨率的方法提高了绝对地址历史记录表缓冲区的索引值的准确性。