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    Method and apparatus for managing write-to-read turnarounds in an early read after write memory system
    1.
    发明授权
    Method and apparatus for managing write-to-read turnarounds in an early read after write memory system 有权
    用于在写入存储器系统之后的早期读取中管理写入读取周转的方法和装置

    公开(公告)号：US07321950B2

    公开(公告)日：2008-01-22

    申请号：US11050021

    申请日：2005-02-03

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    IPC分类号： G06F12/00

    CPC分类号： G06F13/161 ,  G06F13/1647

    摘要： A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

    摘要翻译： 提出了一种用于在写入存储器系统之后的早期读取中管理写入到读取周转的方法和装置。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

    Managing write-to-read turnarounds in an early read after write memory system
    2.
    发明授权
    Managing write-to-read turnarounds in an early read after write memory system 有权
    在写入内存系统之后的早期读取中管理写入阅读的周转时间

    公开(公告)号：US07752379B2

    公开(公告)日：2010-07-06

    申请号：US12349240

    申请日：2009-01-06

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    IPC分类号： G06F12/06 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F13/161 ,  G06F13/1647

    摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

    摘要翻译： 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

    Managing Write-to-Read Turnarounds in an Early Read After Write Memory System
    3.
    发明申请
    Managing Write-to-Read Turnarounds in an Early Read After Write Memory System 有权
    在写入内存系统后的早期读取中管理写入阅读的周转

    公开(公告)号：US20090119442A1

    公开(公告)日：2009-05-07

    申请号：US12349240

    申请日：2009-01-06

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    IPC分类号： G06F12/06

    CPC分类号： G06F13/161 ,  G06F13/1647

    摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

    摘要翻译： 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

    Managing write-to-read turnarounds in an early read after write memory system
    4.
    发明授权
    Managing write-to-read turnarounds in an early read after write memory system 有权
    在写入内存系统之后的早期读取中管理写入阅读的周转时间

    公开(公告)号：US07487318B2

    公开(公告)日：2009-02-03

    申请号：US11851468

    申请日：2007-09-07

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F13/161 ,  G06F13/1647

    摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

    摘要翻译： 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

    Methods and Apparatus for Interfacing a Processor and a Memory
    5.
    发明申请
    Methods and Apparatus for Interfacing a Processor and a Memory 审中-公开
    用于接口处理器和存储器的方法和装置

    公开(公告)号：US20080168206A1

    公开(公告)日：2008-07-10

    申请号：US11620110

    申请日：2007-01-05

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    IPC分类号： G06F13/14

    CPC分类号： G06F13/4059

    摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a first memory; (b) a processor adapted to issue a functional command to the first memory; (c) a translation chip; (d) a cache memory coupled to the translation chip; (e) a first link adapted to couple the processor to the translation chip; and (f) a second link adapted to couple the translation chip to the first memory; and (2) calibrating the first link to transmit data between the processor and cache memory. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）第一存储器的计算机系统; （b）适于向第一存储器发出功能命令的处理器; （c）翻译芯片; （d）耦合到所述平移芯片的高速缓冲存储器; （e）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（f）适于将所述翻译芯片耦合到所述第一存储器的第二链路; 和（2）校准第一链路以在处理器和高速缓冲存储器之间传送数据。 提供了许多其他方面。

    Memory controller to utilize DRAM write buffers
    6.
    发明授权
    Memory controller to utilize DRAM write buffers 有权
    存储器控制器利用DRAM写入缓冲器

    公开(公告)号：US08219745B2

    公开(公告)日：2012-07-10

    申请号：US11002556

    申请日：2004-12-02

    申请人： Mark David Bellows ,  Kent Harold Haselhorst ,  Ryan Abel Heakendorf ,  Paul Allen Ganfield ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Kent Harold Haselhorst ,  Ryan Abel Heakendorf ,  Paul Allen Ganfield ,  Tolga Ozguner

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1673

    摘要： A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.

    摘要翻译： 提供了一种方法，装置和计算机程序来解释存储在动态随机存取存储器（DRAM）写入缓冲器中的数据。 跟踪存储在DRAM写入缓冲器中的数据是困难的。 为了缓解困难，采用缓存行列表。 缓存行列表被保存在存储器控制器中，该存储器控制器被数据移动更新。 该列表允许轻松维护数据而不失一致性。

    Reuse of functional data buffers for pattern buffers in XDR DRAM
    7.
    发明授权
    Reuse of functional data buffers for pattern buffers in XDR DRAM 失效
    在XDR DRAM中重用图形缓冲区的功能数据缓冲区

    公开(公告)号：US07380052B2

    公开(公告)日：2008-05-27

    申请号：US10992378

    申请日：2004-11-18

    申请人： Mark David Bellows ,  Kent Harold Haselhorst ,  Paul Allen Ganfield ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Kent Harold Haselhorst ,  Paul Allen Ganfield ,  Tolga Ozguner

    IPC分类号： G06F12/00

    CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/028

    摘要： A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.

    摘要翻译： 提供了一种方法，装置和计算机程序来重用功能数据缓冲器。 使用极限数据速率（XDR（TMDR））动态随机存取存储器（DRAM），采用测试模式来动态校准数据与时钟。 为了执行此任务，采用数据缓冲器来存储校准模式的数据和命令。 然而，发送和接收校准有不同的程序和要求。 因此，为了减少执行发送和接收校准所需的硬件数量，数据缓冲器使用附加的前端电路来为这两个任务重新使用缓冲器。

    Reuse of functional data buffers for pattern buffers in XDR DRAM
    8.
    发明授权
    Reuse of functional data buffers for pattern buffers in XDR DRAM 失效
    在XDR DRAM中重用图形缓冲区的功能数据缓冲区

    公开(公告)号：US07925823B2

    公开(公告)日：2011-04-12

    申请号：US11875469

    申请日：2007-10-19

    申请人： Mark David Bellows ,  Kent Harold Haselhorst ,  Paul Allen Ganfield ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Kent Harold Haselhorst ,  Paul Allen Ganfield ,  Tolga Ozguner

    IPC分类号： G06F12/00

    CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/028

    摘要： A mechanism is provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.

    摘要翻译： 提供了重用功能数据缓冲器的机制。 使用极限数据速率（XDR™）动态随机存取存储器（DRAM），采用测试模式来动态校准数据与时钟。 为了执行此任务，采用数据缓冲器来存储校准模式的数据和命令。 然而，发送和接收校准有不同的程序和要求。 因此，为了减少执行发送和接收校准所需的硬件数量，数据缓冲器使用附加的前端电路来为这两个任务重新使用缓冲器。

    Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes
    10.
    发明授权
    Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes 有权
    用于利用纠错码生成用于极端数据速率存储器的掩码值和命令的方法和装置

    公开(公告)号：US07287103B2

    公开(公告)日：2007-10-23

    申请号：US11130911

    申请日：2005-05-17

    申请人： Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Charles Ray Johns ,  Peichun Peter Liu

    发明人： Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Charles Ray Johns ,  Peichun Peter Liu

    IPC分类号： G06F3/00 ,  G06F12/00

    CPC分类号： G11C7/1006

    摘要： A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR™ DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.

    摘要翻译： 提供了一种方法，装置和计算机程序产品，用于处理XDR（TM）DRAM存储器系统中的写掩码操作。 本发明消除了对双端口阵列的需要，因为在接收到数据时完成了掩码生成。 掩码计算需要较少的逻辑，因为256个可能的字节值中只有144个被解码。 掩码值生成并存储在掩码数组中。 独立地，写入数据被存储在写入缓冲器中。 掩码值用于生成写掩码命令。 一旦写掩码命令被发出，写入数据和掩码值被发送到多路复用器。 多路器使用掩码值对写入数据进行掩码，以便将掩蔽的数据存储在XDR DRAMS中。