摘要:
A method for depth complexity reduction includes inserting checkpoints between depth sorted object sections in a stream of geometric primitives. In response to receiving a checkpoint while rasterizing primitives for an image region, coverage data stored for the image region is checked to determine whether each pixel in the image region is fully covered. If so, then additional primitives for the image region can be ignored to avoid rendering occluded geometry.
摘要:
A method for rendering graphical objects in a scene to generate a display images includes dividing the geometric primitives of models in a scene among portions or "chunks" of the view space to which the primitives will be rendered, and then rendering geometry referenced to the chunks in series in a common depth buffer. Geometry for a chunk can be rendered, including sophisticated anti-aliasing and translucency computations, using a minimum of memory. Serially rendering object geometry in chunks provides an effective form of compression because pixel fragments can be generated for one chunk at a time and then resolved. Pixel fragments can be resolved in a post-processing step for one chunk while primitives for another chunk are rasterized.
摘要:
Depth buffered anti-aliasing in a real time image generation system utilizing two separate buffers, one for combining attributes of object pixel definitions which are of less than full coverage and another for storing the attributes of each new object pixel definition which is of full coverage and which is closer to the viewpoint than any attributes currently stored. If the depth value in the partial buffer is closer the viewpoint than that in the full buffer, a set of attributes is output which is a weighted mixture of those stored in the two buffers.
摘要:
A system for accessing texture data in a graphics rendering system allows texture data to be stored in memories with high latency or in a compressed format. The system utilizes a texture cache to temporarily store blocks of texture data retrieved from an external memory during rendering operations. In one implementation, geometric primitives are stored in a queue long enough to absorb the latency of fetching and possibly decompressing a texture block. The geometric primitives are converted into texture block references, and these references are used to fetch texture blocks from memory. A rasterizer rasterizes each geometric primitives as the necessary texture data becomes available in the texture cache. In another implementation, geometric primitives are converted into pixels, including a pixel address, color data, and a texture request. These pixels are stored in a queue long enough to absorb the latency of a texture block fetch. The texture requests are read from the queue and used to fetch the appropriate texture blocks. As texture data becomes available in the texture cache, the texture data is sampled as necessary and combined with the pixel data read from the queue to compute output pixels.
摘要:
An image generator architecture in which tri-level fixed interleave processing provides medium grain parallelism for polygon, tiling, and pixel operations. Input data at each stage are divided into spatially distributed subsets that are interleaved among parallel processors using a fixed, precalculated mapping that minimizes correlation of local scene complexity with any one processor. The present tri-level fixed interleave processing architecture divides a processing task into a pseudo-random, fixed interleaved pattern of regions that are assigned to different processors. Each processor processes many of these randomly located regions. The assignment of processors to regions is a fixed repeating pattern. The highest level of fixed interleave processing is the allocation of fixed-size database regions (area modules) to polygon processors. The next level relates to image sub-region fixed interleave processing. At this level, the displayed image is divided into small sub-regions that are assigned to tilers in a pseudo-random, but fixed manner. This levels the load across all pixel processors. Typically, tilers process a large contiguous area of the image. The present invention uses small sub-regions (64.times.64 pixels) and assigns many sub-regions from different channels to a single tiler. Each tiler maintains equal loading .even with localized regions of high pixel processing. The third level relates to two-by-two pixel, fixed interleave processing. The image is further divided into 2.times.2 pixel blocks spread across multiple pixel operators on a tiler. This fine grain parallelism, in a fixed pseudo-random orientation, ensures equal loading across all pixel processors. The second aspect of the present invention is the use of polygon and pixel distribution buses. Maximum image generator configurability, expansion, and efficient processing is required for a variety of simulator configurations used in networked training environments. To accomplish this, distribution buses are implemented between all graphics processing stages.
摘要:
Techniques and tools for rating computer products are described. For example, software ratings are based on subjective evaluations to determine computer system requirements for a positive user experience, while a computer running a capability tool rates a computer system's (or hardware component's) ability to run software. A capability rating for hardware is determined by comparing a set of features and performance results with capability rating requirements. In another aspect, a capability rating is communicated using a standardized presentation. In another aspect, capability rating level requirements are proposed (e.g., by a ratings board) and then finalized. A capability rating level is determined for computer products (e.g., by a testing organization) based on the finalized requirements and analysis of the products (e.g., by a computer running a capability tool). In another aspect, a software system comprises an inventory module, a performance testing module, and an inventory and performance evaluator module.
摘要:
In a graphics rendering system, an apparatus for resolving depth sorted lists of pixel fragments includes color and alpha accumulators for computing color and alpha values from the pixel fragments in a fragment list. Pixel fragments include color, alpha, coverage data. The coverage data describes how a geometric primitive covers sub-pixel regions of a pixel using a coverage mask. Pixel circuitry according to a clock-optimized approach includes separate color and alpha accumulators for computing color and alpha values for sub-pixel regions of a pixel. The accumulated color values are then summed and scaled to compute final color values for a pixel. To reduce hardware requirements, pixel circuitry in a hardware-optimized approach recognizes that some pixel regions have common accumulated alpha values as each fragment layer is processed. As such, color contributions for fragment layers can be computed using a single color accumulation operation for a pixel region having common alpha values.
摘要:
In a real time image generation system opaque or planar object pixels are defined by at least a color attribute and a depth value and volumetric pixels are defined by at least a color attribute, a depth value and an opacity gradient value. A volumetric data buffer is provided for storing attributes and values associated with volumetric pixels and the volumetric items are processed first to load that buffer. Successive object pixel definitions are then read and the depth value of each current object pixel definition is compared with the depth value in the buffer and a relative weight for the volumetric effect is calculated as a function of the relative depth values and the corresponding volume gradient value. The color attributes of the object pixel and the volumetric data are then mixed as a function of the relative weighting to obtain a result color attribute which is output as the color for the respective pixel.
摘要:
Techniques and tools for rating computer products are described. For example, software ratings are based on subjective evaluations to determine computer system requirements for a positive user experience, while a computer running a capability tool rates a computer system's (or hardware component's) ability to run software. A capability rating for hardware is determined by comparing a set of features and performance results with capability rating requirements. In another aspect, a capability rating is communicated using a standardized presentation. In another aspect, capability rating level requirements are proposed (e.g., by a ratings board) and then finalized. A capability rating level is determined for computer products (e.g., by a testing organization) based on the finalized requirements and analysis of the products (e.g., by a computer running a capability tool). In another aspect, a software system comprises an inventory module, a performance testing module, and an inventory and performance evaluator module.
摘要:
A graphics rendering chip serially renders a stream of geometric primitives to image regions called chunks. A set-up processor in the chip parses rendering commands and the stream of geometric primitives and computes edge equation parameters. A scan-convert processor receives the edge equation parameters from the set-up processor and scan converts the geometric primitives to produce pixel records and fragment records. An internal, double-buffered pixel buffer stores pixel records for fully covered pixel addresses and also stores references to fragment lists stored in a fragment buffer. A pixel engine performs hidden surface removal and controls storage of pixel and fragment records to the pixel and fragment buffers, respectively. An anti-aliasing engine resolves pixel data for one pixel buffer while the pixel engine fills the other pixel buffer with pixel data for the next chunk.