利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

41 条记录 (耗时 0.037 秒)

    Method and system for accessing texture data in environments with high latency in a graphics rendering system
    1.
    发明授权
    Method and system for accessing texture data in environments with high latency in a graphics rendering system 失效
    用于在图形渲染系统中访问具有高延迟的环境中的纹理数据的方法和系统

    公开(公告)号：US5880737A

    公开(公告)日：1999-03-09

    申请号：US670553

    申请日：1996-06-27

    申请人： Kent E. Griffin ,  Mark L. Kenworthy ,  James E. Veres ,  Joseph W. Chauvin ,  Michael A. Toelle ,  Howard Good

    发明人： Kent E. Griffin ,  Mark L. Kenworthy ,  James E. Veres ,  Joseph W. Chauvin ,  Michael A. Toelle ,  Howard Good

    IPC分类号： G06T11/00 ,  G06T13/00 ,  G06T15/00 ,  G06T15/20 ,  G06T15/60 ,  G06T11/40

    CPC分类号： G06T11/001 ,  G06T11/40 ,  G06T13/80 ,  G06T15/005 ,  G06T15/04 ,  G06T15/60

    摘要： A system for accessing texture data in a graphics rendering system allows texture data to be stored in memories with high latency or in a compressed format. The system utilizes a texture cache to temporarily store blocks of texture data retrieved from an external memory during rendering operations. In one implementation, geometric primitives are stored in a queue long enough to absorb the latency of fetching and possibly decompressing a texture block. The geometric primitives are converted into texture block references, and these references are used to fetch texture blocks from memory. A rasterizer rasterizes each geometric primitives as the necessary texture data becomes available in the texture cache. In another implementation, geometric primitives are converted into pixels, including a pixel address, color data, and a texture request. These pixels are stored in a queue long enough to absorb the latency of a texture block fetch. The texture requests are read from the queue and used to fetch the appropriate texture blocks. As texture data becomes available in the texture cache, the texture data is sampled as necessary and combined with the pixel data read from the queue to compute output pixels.

    摘要翻译： 用于在图形渲染系统中访问纹理数据的系统允许纹理数据以高延迟或压缩格式存储在存储器中。 该系统利用纹理缓存临时存储在渲染操作期间从外部存储器检索的纹理数据块。 在一个实现中，几何基元被存储在队列中足够长的时间以吸收提取的延迟并且可能解压缩纹理块。 几何基元被转换为纹理块引用，这些引用用于从内存中获取纹理块。 当纹理缓存中必需的纹理数据变得可用时，光栅化器会栅格化每个几何图元。 在另一个实现中，几何基元被转换成像素，包括像素地址，颜色数据和纹理请求。 这些像素被存储在足够长的队列中以吸收纹理块提取的等待时间。 从队列中读取纹理请求，并用于获取适当的纹理块。 随着纹理数据在纹理高速缓存中变得可用，纹理数据根据需要进行采样，并与从队列读取的像素数据组合以计算输出像素。

    Method and apparatus for resolving pixel data in a graphics rendering system
    5.
    发明授权
    Method and apparatus for resolving pixel data in a graphics rendering system 失效
    用于解析图形渲染系统中的像素数据的方法和装置

    公开(公告)号：US5949428A

    公开(公告)日：1999-09-07

    申请号：US672694

    申请日：1996-06-27

    申请人： Michael A. Toelle ,  Mark L. Kenworthy

    发明人： Michael A. Toelle ,  Mark L. Kenworthy

    IPC分类号： G06T11/00 ,  G06T13/00 ,  G06T15/00 ,  G06T15/20 ,  G06T15/60 ,  G06F15/00

    CPC分类号： G06T11/001 ,  G06T11/40 ,  G06T13/80 ,  G06T15/005 ,  G06T15/04 ,  G06T15/60

    摘要： In a graphics rendering system, an apparatus for resolving depth sorted lists of pixel fragments includes color and alpha accumulators for computing color and alpha values from the pixel fragments in a fragment list. Pixel fragments include color, alpha, coverage data. The coverage data describes how a geometric primitive covers sub-pixel regions of a pixel using a coverage mask. Pixel circuitry according to a clock-optimized approach includes separate color and alpha accumulators for computing color and alpha values for sub-pixel regions of a pixel. The accumulated color values are then summed and scaled to compute final color values for a pixel. To reduce hardware requirements, pixel circuitry in a hardware-optimized approach recognizes that some pixel regions have common accumulated alpha values as each fragment layer is processed. As such, color contributions for fragment layers can be computed using a single color accumulation operation for a pixel region having common alpha values.

    摘要翻译： 在图形渲染系统中，用于解析像素片段的深度排序列表的装置包括用于从片段列表中的像素片段计算颜色和α值的颜色和α累加器。 像素片段包括彩色，alpha，coverage数据。 覆盖数据描述几何图元如何使用覆盖掩码覆盖像素的子像素区域。 根据时钟优化方法的像素电路包括用于计算像素的子像素区域的颜色和α值的单独的颜色和α累加器。 然后将累加的颜色值相加和缩放以计算像素的最终颜色值。 为了降低硬件要求，硬件优化方法中的像素电路识别出，随着每个片段层被处理，某些像素区域具有共同的累积alpha值。 因此，可以使用对具有公共α值的像素区域的单个颜色累积操作来计算片段层的颜色贡献。

    METHOD AND SYSTEM FOR DEFINING AND CONTROLLING ALGORITHMIC ELEMENTS IN A GRAPHICS DISPLAY SYSTEM
    6.
    发明申请
    METHOD AND SYSTEM FOR DEFINING AND CONTROLLING ALGORITHMIC ELEMENTS IN A GRAPHICS DISPLAY SYSTEM 有权
    用于在图形显示系统中定义和控制算法元素的方法和系统

    公开(公告)号：US20100039430A1

    公开(公告)日：2010-02-18

    申请号：US12604102

    申请日：2009-10-22

    申请人： Charles N. Boyd ,  Michael A. Toelle

    发明人： Charles N. Boyd ,  Michael A. Toelle

    IPC分类号： G06T15/50

    CPC分类号： G06T15/005

    摘要： An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.

    摘要翻译： 提供了一种能够实现3D芯片的可编程性的API，其中由开发者编写的编程或算法元素可以被下载到芯片，从而对芯片进行编程以执行这些算法。 开发人员将可下载的例程写入3D图形芯片。 还提供了一组与已经为开发人员编程的API相关联的算法元素，可以下载到可编程芯片以提高性能。 因此，开发人员可以将预先存在的API对象下载到3D图形芯片。 开发人员坚持使用特定格式来打包一个由3D图形芯片实现的算法元素或指令集。 开发人员通过参考3D图形芯片了解的“令牌”列表将指令集打包成数组。 这个数组依次被正确地映射到3D图形芯片，用于由3D图形芯片实现算法元素。

    SYSTEMS AND METHODS FOR PROVIDING CONTROLLABLE TEXTURE SAMPLING
    7.
    发明申请
    SYSTEMS AND METHODS FOR PROVIDING CONTROLLABLE TEXTURE SAMPLING 有权
    提供可控纹理采样的系统和方法

    公开(公告)号：US20080122856A1

    公开(公告)日：2008-05-29

    申请号：US11938113

    申请日：2007-11-09

    申请人： CHARLES N. BOYD ,  Michael A. Toelle

    发明人： CHARLES N. BOYD ,  Michael A. Toelle

    IPC分类号： G09G5/00

    CPC分类号： G06T15/04

    摘要： Systems and methods are provided for controlling texture sampling in connection with computer graphics in a computer system. In various embodiments, improved mechanisms for controlling texture sampling are provided that enable 3-D accelerator hardware to greatly increase the level of realism in rendering, including improved mechanisms for (1) motion blur; (2) generating anisotropic surface reflections (3) generating surface self-shadowing (4) ray-cast volumetric sampling (4) self-shadowed volumetric rendering and (5) self-shadowed volumetric ray-casting. In supplementing existing texture sampling techniques, parameters for texture sampling may be replaced and/or modified.

    摘要翻译： 提供系统和方法用于控制与计算机系统中的计算机图形相关的纹理采样。 在各种实施例中，提供了用于控制纹理采样的改进机制，其使3-D加速器硬件能够大大增加渲染中的逼真度，包括（1）运动模糊的改进机制; （2）产生各向异性表面反射（3）产生表面自阴影（4）射线体积采样（4）自阴影体积渲染和（5）自阴影体积射线铸造。 在补充现有的纹理采样技术中，用于纹理采样的参数可以被替换和/或修改。

    API communications for vertex and pixel shaders
    8.
    发明授权
    API communications for vertex and pixel shaders 有权

    公开(公告)号：US07116332B2

    公开(公告)日：2006-10-03

    申请号：US10981865

    申请日：2004-11-05

    申请人： Charles F. Boyd ,  Michael A. Toelle

    发明人： Charles F. Boyd ,  Michael A. Toelle

    IPC分类号： G09G5/36 ,  G09G5/37 ,  G06F13/00 ,  G06T15/50

    CPC分类号： G06T15/00 ,  G06T15/005 ,  G06T15/80 ,  G06T2210/32

    摘要： A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.

    Method and system for providing a unified API for both 2D and 3D graphics objects
    9.
    发明授权
    Method and system for providing a unified API for both 2D and 3D graphics objects 有权
    为2D和3D图形对象提供统一的API的方法和系统

    公开(公告)号：US06831635B2

    公开(公告)日：2004-12-14

    申请号：US09796885

    申请日：2001-03-01

    申请人： Charles N. Boyd ,  Jeff M. J. Noyle ,  Michael A. Toelle

    发明人： Charles N. Boyd ,  Jeff M. J. Noyle ,  Michael A. Toelle

    IPC分类号： G06F1700

    CPC分类号： G06F9/541

    摘要： A method for controlling the algorithmic elements in 3D graphics systems via an improved 3D graphics API is provided. In one aspect, the invention unifies separately provided 2D and 3D graphics APIs into a single graphics interface, thereby eliminating redundancy of functionality and unnecessary data types. As a result, a single mapping to various graphics objects replaces redundant mappings. A single texture download that optimizes the use of different graphics hardware is provided. A single instruction for effecting a resolution change is also provided.

    摘要翻译： 提供了一种通过改进的3D图形API来控制3D图形系统中的算法元素的方法。 在一个方面，本发明将单独提供的2D和3D图形API统一为单个图形接口，从而消除功能冗余和不必要的数据类型。 因此，对各种图形对象的单一映射将替代冗余映射。 提供了优化不同图形硬件使用的单一纹理下载。 还提供了一个用于进行分辨率改变的指令。

    Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques
    10.
    发明授权
    Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权
    将算法元素下载到协处理器的系统和方法以及相应的技术

    公开(公告)号：US08274517B2

    公开(公告)日：2012-09-25

    申请号：US10986586

    申请日：2004-11-12

    申请人： Charles N. Boyd ,  Michele B. Boland ,  Michael A. Toelle ,  Anantha Rao Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen H. Wright

    发明人： Charles N. Boyd ,  Michele B. Boland ,  Michael A. Toelle ,  Anantha Rao Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen H. Wright

    IPC分类号： G06T1/00 ,  G06T15/00

    CPC分类号： G06F9/325 ,  G06F9/3842 ,  G06F9/3879 ,  G06T15/005 ,  G06T15/80

    摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.

    摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点 着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。