摘要:
A superscalar microprocessor includes a combination floating point and multimedia unit. The floating point and multimedia unit includes one set of registers. The multimedia core and floating point core share the one set of registers. Each register as a type field associated with the register. The type field identifies whether the associated register contains valid data and whether the data is of multimedia type or floating point type. If the register stores floating point type data, the type field further indicates which of a plurality of floating point types the register stores such as: zero, infinity and normal. The floating point core relies on the type field to identify special floating point numbers such as zero and infinity. To ensure predictable results when a floating point instruction is executed subsequent to a multimedia instruction, a retyping algorithm retypes registers typed as multimedia type when the first floating point instruction subsequent to a multimedia instruction is executed. The retyping algorithm reads each register and reclassifies the registers classified as multimedia type. The reclassification algorithm classifies the contents of the register interpreted as floating point data.
摘要:
A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or multiple operations, when the reduced-bit mode is indicated.
摘要:
A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into one or more full-bit operations, when the full-bit mode is indicated, or one or more reduced-bit operations, when the reduced-bit mode is indicated.
摘要:
A superscalar microprocessor appends a tag value to each floating point number. The tag value indicates whether the corresponding floating point number is a normal floating point number or a special floating point number. Additionally, the tag value indicates the type of special floating point number represented by the corresponding floating point number. The tag value is stored with the floating point number in a register file of the floating point unit. Tag values are also generated for floating point numbers read from memory. When a floating point core of a floating point unit receives operands from either the register file or memory, the floating point core examines the tag values to determine whether each operand is a normal floating point number or a special floating point number. If either operand is a special floating point number, the floating point core determines the type of special floating point number and applies any applicable special rules. By appending tag values to each floating point number, the floating point unit can quickly determine which floating point numbers are special floating point numbers and the type of special floating point number. This reduces the time necessary to identify floating point numbers and expedites the execution of floating point instructions.
摘要:
A functional unit of a processor may be configured to operate on instructions as either a single, wide functional unit or as multiple, independent narrower units. For example, an execution unit may be scheduled to execute an instruction as a single double-wide execution unit or as two independently schedulable single-wide execution units. Functional unit portions may be independently schedulable for execution of instructions operating on a first data type (e.g. SISD instructions). For single-wide instructions, functional unit portions may be scheduled independently. An issue lock mechanism may lock functional unit portions together so that they form a single multi-wide functional unit. For certain multi-wide instructions (e.g. certain SIMD instructions), an instruction operating on a multi-wide or vector data type may be scheduled so that the full multi-wide operation is performed concurrently by functional unit portions locked together as a one wide functional unit.
摘要:
According to one general aspect, an apparatus may include a load/store unit, an execution unit, and a first and a second data path. The load/store unit may be configured to load/store data from/to a memory and transmit the data to/from an execution unit, wherein the data includes a plurality of elements. The execution unit may be configured to perform an operation upon the data. The load/store unit may be configured to transmit the data to/from the execution unit via either a first data path configured to communicate, without transposition, the data between the load/store unit and the execution unit, or a second data path configured to communicate, with transposition, the data between the load/store unit and the execution unit, wherein transposition includes dynamically distributing portions of the data amongst a plurality of elements according to an instruction.
摘要:
A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or multiple operations, when the reduced-bit mode is indicated.
摘要:
Reconfiguring a register file using a rename table having a plurality of fields that indicate fracture information about a source register of an instruction for instructions which have narrow to wide dependencies.
摘要:
According to one general aspect, an apparatus may include a load/store unit, an execution unit, and a first and a second data path. The load/store unit may be configured to load/store data from/to a memory and transmit the data to/from an execution unit, wherein the data includes a plurality of elements. The execution unit may be configured to perform an operation upon the data. The load/store unit may be configured to transmit the data to/from the execution unit via either a first data path configured to communicate, without transposition, the data between the load/store unit and the execution unit, or a second data path configured to communicate, with transposition, the data between the load/store unit and the execution unit, wherein transposition includes dynamically distributing portions of the data amongst a plurality of elements according to an instruction.