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1.发明授权Method and system for generating an engine position dependent output control signal 失效用于产生与发动机位置相关的输出控制信号的方法和系统
公开(公告)号：US5628292A
公开(公告)日：1997-05-13
申请号：US625378
申请日：1996-04-01
CPC分类号： F02D41/009 , F02P7/0775 , G01P3/489
摘要： A method and system for generating a position dependent output control signal. The position of a rotating machine, such as an internal combustion engine, is sensed and a corresponding position signal is generated. The position signal is processed to obtain the position dependent output control signal including a first control signal and a second control signal. The first control signal represents a sector of the rotating machine, and the second control signal represents the absolute position within the sector.
摘要翻译： 一种用于产生与位置有关的输出控制信号的方法和系统。 检测旋转机器（例如内燃机）的位置，并产生对应的位置信号。 处理位置信号以获得包括第一控制信号和第二控制信号的与位置相关的输出控制信号。 第一控制信号表示旋转机器的扇区，第二控制信号表示扇区内的绝对位置。
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2.发明授权Queued port data controller for microprocessor-based engine control applications 失效排队端口数据控制器，用于基于微处理器的发动机控制应用公开(公告)号：US06381532B1
公开(公告)日：2002-04-30
申请号：US09665094
申请日：2000-09-20
申请人： Gary T. Bastian , Kevin M. Rishavy , Martin G. Gravenstein , Robert L. Anderson , Rollie M. Fisher , Raymond A. Stevens , Samuel J. Guido
发明人： Gary T. Bastian , Kevin M. Rishavy , Martin G. Gravenstein , Robert L. Anderson , Rollie M. Fisher , Raymond A. Stevens , Samuel J. Guido
IPC分类号： G06F1310
CPC分类号： G06F13/4059
摘要： An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.
摘要翻译： 一种发动机控制系统，包括与数据总线可操作地通信的主处理器和用于通信发动机操作参数的多个外围设备。 每个外围设备包括用于存储对应的多个外围设备中的每一个的通信参数的第一和第二事务寄存器。 控制系统还包括排队端口速率寄存器（QRR），其包括与多个外围设备进行操作通信的存储器单元，用于根据第一和第二事务寄存器存储用于传输到多个外围设备的数据。 该系统还包括与多个外围设备中的每一个操作通信的外围计数器。 周边计数器适于询问多个外围设备中的每一个，并且当数据已被写入外围设备之一时，根据存储器单元数据来更新外围设备。
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3.发明授权I/O multiplexer and pin controller with serial and parallel capabilities for microprocessor based engine control 失效I / O多路复用器和引脚控制器，具有串行和并行功能，用于基于微处理器的发动机控制公开(公告)号：US06978340B2
公开(公告)日：2005-12-20
申请号：US09774230
申请日：2001-01-30
CPC分类号： G06F13/4291
摘要： A controller 12 has an I/O crossover switching network 14, an optional I/O network expansion 16, a plurality of serial I/O shifters 18, a clock generator 20 and I/O control logic 22. The I/O crossover-switching network 14 is also referred to as an I/O multiplexer. Serial data may be transferred between a serial I/O shifter and an external device by way of a dedicated serial data pin (SDATA) 24 or an optional alternate pathway 26 which uses one of a plurality of parallel pins 28. The optional alternate pathway 26 can be used when pins 28 are unavailable or to reduce the number of pins on the device 12. The controller is shown to communicate with an external device 30 also having parallel pins 32. While a single device 30 is shown, the external device 30 can be any number of a plurality of devices having serial and parallel signal pathways that is controlled by the microprocessor 10 of the present invention.
摘要翻译： 控制器12具有I / O交叉交换网络14，可选的I / O网络扩展16，多个串行I / O移位器18，时钟发生器20和I / O控制逻辑22。 I / O交换交换网络14也称为I / O多路复用器。 串行数据可以通过专用串行数据引脚（SDATA）24或使用多个并行引脚28之一的可选的备用通路26在串行I / O移位器和外部设备之间传输。 当引脚28不可用或减少器件12上的引脚数时，可以使用可选的备选路径26。 控制器被示出为与具有并行销32的外部设备30通信。 虽然示出了单个设备30，但是外部设备30可以是具有由本发明的微处理器10控制的串行和并行信号路径的多个设备的任何数量。
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公开(公告)号：US08156269B2
公开(公告)日：2012-04-10
申请号：US12756262
申请日：2010-04-08
CPC分类号： H03K5/086 , F02D37/02 , F02D41/008 , F02D41/2435 , F02D41/28
摘要： A system that includes a multiplexer having an output selectively coupled to a plurality of inputs, a bus coupled to the output of the multiplexer, and first and second circuits configured to generate first and second digital signals, respectively. The first digital signal is related to a rotational angle of a crankshaft at a first point in time, and the second digital signal is related to a value of parameter at the first point in time, wherein the parameter is one other than the rotational angle of the crankshaft. The first and second circuits are coupled directly or indirectly to first and second inputs of the multiplexer.
摘要翻译： 一种系统，其包括多路复用器，其具有选择性地耦合到多个输入的输出，耦合到所述多路复用器的输出的总线，以及被配置为分别产生第一和第二数字信号的第一和第二电路。 第一数字信号与第一时间点的曲轴的旋转角度相关，第二数字信号与第一时间点的参数值相关，其中参数是与第一时间点的旋转角度 曲轴。 第一和第二电路直接或间接耦合到多路复用器的第一和第二输入端。
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公开(公告)号：US20100191438A1
公开(公告)日：2010-07-29
申请号：US12756262
申请日：2010-04-08
IPC分类号： G06F19/00
CPC分类号： H03K5/086 , F02D37/02 , F02D41/008 , F02D41/2435 , F02D41/28
摘要： A system that includes a multiplexer having an output selectively coupled to a plurality of inputs, a bus coupled to the output of the multiplexer, and first and second circuits configured to generate first and second digital signals, respectively. The first digital signal is related to a rotational angle of a crankshaft at a first point in time, and the second digital signal is related to a value of parameter at the first point in time, wherein the parameter is one other than the rotational angle of the crankshaft. The first and second circuits are coupled directly or indirectly to first and second inputs of the multiplexer.
摘要翻译： 一种系统，其包括多路复用器，其具有选择性地耦合到多个输入的输出，耦合到所述多路复用器的输出的总线，以及被配置为分别产生第一和第二数字信号的第一和第二电路。 第一数字信号与第一时间点的曲轴的旋转角度相关，第二数字信号与第一时间点的参数值相关，其中参数是与第一时间点的旋转角度 曲轴。 第一和第二电路直接或间接耦合到多路复用器的第一和第二输入端。
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公开(公告)号：US08711023B2
公开(公告)日：2014-04-29
申请号：US12612353
申请日：2009-11-04
申请人： Samuel J. Guido , Jeremy Brodt , Jeff Sieber
发明人： Samuel J. Guido , Jeremy Brodt , Jeff Sieber
IPC分类号： H03M1/12
CPC分类号： F02D41/263 , F02D35/027 , F02D41/1454 , F02D41/28
摘要： A method and apparatus for detecting an event and sampling first value from a pin in response to the event. For example, the event is identified by a signal object of a plurality of signal objects stored in a memory. Each signal object of the plurality of signal objects identifies a single analog input pin and a trigger.
摘要翻译： 一种用于响应于事件检测事件并从引脚采样第一值的方法和装置。 例如，事件由存储在存储器中的多个信号对象的信号对象来识别。 多个信号对象的每个信号对象识别单个模拟输入引脚和触发器。
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公开(公告)号：US08010722B2
公开(公告)日：2011-08-30
申请号：US12622609
申请日：2009-11-20
CPC分类号： H03K5/082 , F02D41/20 , F02D41/2403 , H04L12/40006
摘要： An apparatus is disclosed that includes first and second circuits coupled together via a bus, an input pin configured to receive an analog input signal, a digital-to-analog (DAC) convertor configured to convert a multibit reference signal into an analog reference signal, a comparator circuit coupled to the bus, an output of the DAC and to the input pin. The comparator circuit is configured to receive the analog reference signal from the DAC and the analog input signal, and configured to generate a first digital signal set to a first state if the analog reference signal is greater in magnitude than the analog input signal, or set to a second state if analog reference signal is lower in magnitude than the analog input signal. The comparator circuit is also configured to transmit the first digital signal to the first circuit via the bus. The first circuit in turn is configured to receive the first digital signal. In response to receiving the first digital signal, the first circuit is configured to generate a second digital signal set to the first or second state depending on whether the received first digital signal is set to the first or second state. The second circuit is configured to receive the second digital signal from the first circuit via the bus.
摘要翻译： 公开了一种装置，其包括经由总线耦合在一起的第一和第二电路，被配置为接收模拟输入信号的输入引脚，被配置为将多位参考信号转换为模拟参考信号的数模转换器（DAC） 耦合到总线的比较器电路，DAC的输出和输入引脚。 比较器电路被配置为从DAC和模拟输入信号接收模拟参考信号，并且被配置为如果模拟参考信号的幅度大于模拟输入信号，则将第一数字信号设置为第一状态，或者设置 如果模拟参考信号的幅度比模拟输入信号低，则到第二状态。 比较器电路还被配置为经由总线将第一数字信号发送到第一电路。 第一电路又被配置为接收第一数字信号。 响应于接收到第一数字信号，第一电路被配置为根据接收到的第一数字信号是否被设置为第一或第二状态来生成设置为第一或第二状态的第二数字信号。 第二电路被配置为经由总线从第一电路接收第二数字信号。
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公开(公告)号：US20100114376A1
公开(公告)日：2010-05-06
申请号：US12264538
申请日：2008-11-04
CPC分类号： F02D41/263 , F02D41/20 , F02D41/26 , F02P5/15 , Y02T10/46
摘要： An apparatus and method of scheduling signals. In one embodiment, the method includes a first circuit receiving a first plurality of reference values. The first circuit selects a reference value from the first plurality according to a first reference identifier (ID) that is stored in memory. The first circuit compares the selected reference value to a first match value.
摘要翻译： 一种调度信号的装置和方法。 在一个实施例中，该方法包括接收第一多个参考值的第一电路。 第一电路根据存储在存储器中的第一参考标识符（ID）选择来自第一多个的参考值。 第一电路将所选择的参考值与第一匹配值进行比较。
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公开(公告)号：US08446943B2
公开(公告)日：2013-05-21
申请号：US12766204
申请日：2010-04-23
CPC分类号： H03K7/08 , H04B3/542 , H04B14/026
摘要： A method and apparatus for communicating over a power line. In one embodiment of the method, a first PWM waveform signal is generated, wherein a duty cycle of the first PWM waveform signal is proportional to an amplitude of a first analog signal. A first sinusoidal waveform signal is also generated, which has a first frequency. The first sinusoidal waveform signal is modulated in relation to the first PWM waveform signal. The modulated first sinusoidal waveform signal is transmitted to a circuit via a power conductor that couples a power source to the circuit. The circuit in turn generates a demodulated signal by demodulating the modulated first sinusoidal waveform signal.
摘要翻译： 一种用于通过电力线通信的方法和装置。 在该方法的一个实施例中，产生第一PWM波形信号，其中第一PWM波形信号的占空比与第一模拟信号的幅度成比例。 还产生第一正弦波形信号，其具有第一频率。 相对于第一PWM波形信号调制第一正弦波形信号。 经调制的第一正弦波形信号通过将电源耦合到电路的电源导体传输到电路。 电路又通过解调调制的第一正弦波形信号来产生解调信号。
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公开(公告)号：US20110106415A1
公开(公告)日：2011-05-05
申请号：US12612353
申请日：2009-11-04
申请人： Samuel J. Guido , Jeremy Brodt , Jeff Sieber
发明人： Samuel J. Guido , Jeremy Brodt , Jeff Sieber
IPC分类号： F02D45/00
CPC分类号： F02D41/263 , F02D35/027 , F02D41/1454 , F02D41/28
摘要： A method and apparatus for detecting an event and sampling first value from a pin in response to the event. A plurality of signal objects is stored in a memory. Each signal object identifies a single analog input pin and a trigger.
摘要翻译： 一种用于响应于事件检测事件并从引脚采样第一值的方法和装置。 多个信号对象被存储在存储器中。 每个信号对象标识一个模拟输入引脚和一个触发器。
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