公开(公告)号：US07689884B2

公开(公告)日：2010-03-30

申请号：US11789269

申请日：2007-04-23

申请人： Markus Seuring

发明人： Markus Seuring

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318561 ,  G01R31/318563

摘要： An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture. In particular, the provided approach enables the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test.

摘要翻译： 提供了集成芯片架构，其允许有效测试集成芯片架构中包含的多个核心。 特别地，所提供的方法使得测试时间和所需的输入/输出测试引脚的数量几乎与包含在多核芯片中的核心数量无关。 所提出的实施例提供了多芯片架构，其允许并行地向多个核提供输入数据以同时测试多个核，并且分析所得到的多个测试输出。 作为该分析的结果，实施例可以在芯片上存储尚未成功通过测试的那些核心的指示。

公开(公告)号：US07673208B2

公开(公告)日：2010-03-02

申请号：US11789369

申请日：2007-04-23

申请人： Markus Seuring

发明人： Markus Seuring

IPC分类号： G06F11/00 ,  G01R31/28

CPC分类号： G06F11/2242

摘要： An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture and storing corresponding diagnosis data which include an indication of the failure-causing test data and the corresponding test analysis data. Embodiments are provided which enable that the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test, together with respective diagnosis data.

摘要翻译： 提供了一种集成芯片架构，其允许有效测试集成芯片架构中包括的多个核心并存储相应的诊断数据，其中包括故障测试数据和相应的测试分析数据的指示。 实施例使得测试时间和所需输入/输出测试引脚的数量几乎与包含在多芯片芯片中的核心数量无关。 所提出的实施例提供了多芯片架构，其允许并行地向多个核提供输入数据以同时测试多个核，并且分析所得到的多个测试输出。 作为该分析的结果，实施例可以在芯片上存储尚未成功通过测试的那些核心的指示以及相应的诊断数据。

公开(公告)号：US07653845B2

公开(公告)日：2010-01-26

申请号：US11484157

申请日：2006-07-11

申请人： Siegfried Kay Hesse ,  Markus Seuring ,  Thomas Herrmann

发明人： Siegfried Kay Hesse ,  Markus Seuring ,  Thomas Herrmann

IPC分类号： G11C29/00

CPC分类号： G11C29/16

摘要： An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational testing. The plurality of test algorithms includes a fault detection test algorithm to perform operational testing of the on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault. The plurality of test algorithms further includes a fault location test algorithm to perform operational testing of the on-chip memory in order to detect and locate a memory fault. Further, a method to perform a memory built-in self test and an MBIST (Memory Built-In Self Test) control circuit template are provided.

摘要翻译： 提供了一种集成电路芯片，其包括片上存储器和测试电路。 测试电路被配置为执行片上存储器的操作测试。 测试电路包括控制器，其被配置为执行从多个测试算法中的选择以执行操作测试。 多个测试算法包括故障检测测试算法，以对片内存储器进行操作测试，以便检测是否存在存储器故障，而不定位存储器故障。 多个测试算法还包括故障定位测试算法，以执行片上存储器的操作测试，以便检测和定位存储器故障。 此外，提供了执行存储器内置自检和MBIST（存储器内置自检）控制电路模板的方法。

公开(公告)号：US09885752B2

公开(公告)日：2018-02-06

申请号：US13816725

申请日：2010-08-12

申请人： Markus Seuring ,  Michael Braun

发明人： Markus Seuring ,  Michael Braun

IPC分类号： G01R31/3177 ,  G01R31/3185 ,  G01R31/317

CPC分类号： G01R31/3177 ,  G01R31/31703 ,  G01R31/31704 ,  G01R31/318547 ,  G01R31/318561 ,  G01R31/318566 ,  G01R31/318569

摘要： A test apparatus for generating reference scan chain test data comprises a test pattern generator and an output data modifier. The test pattern generator modifies a scan chain test input bit sequence by replacing a predefined number of start bits of the scan chain test input bit sequence by a predefined start bit sequence. Further, the test pattern generator provides the modified scan chain test input bit sequence to a device under test. The output data modifier modifies a scan chain test output bit sequence received from the device under test and caused by the modified scan chain test input bit sequence. The scan chain test output bit sequence is modified by replacing a predefined number of end bits of the scan chain test output bit sequence by a predefined end bit sequence to obtain the reference scan chain test data.

公开(公告)号：US20080148117A1

公开(公告)日：2008-06-19

申请号：US11789269

申请日：2007-04-23

申请人： Markus Seuring

发明人： Markus Seuring

IPC分类号： G01R31/28

CPC分类号： G01R31/318561 ,  G01R31/318563

摘要： An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture. In particular, the provided approach enables the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test.

摘要翻译： 提供了集成芯片架构，其允许有效测试集成芯片架构中包含的多个核心。 特别地，所提供的方法使得测试时间和所需的输入/输出测试引脚的数量几乎与包含在多核芯片中的核心数量无关。 所提出的实施例提供了多芯片架构，其允许并行地向多个核提供输入数据以同时测试多个核，并且分析所得到的多个测试输出。 作为该分析的结果，实施例可以在芯片上存储尚未成功通过测试的那些核心的指示。

公开(公告)号：US08307249B2

公开(公告)日：2012-11-06

申请号：US12709565

申请日：2010-02-22

申请人： Markus Seuring ,  Kay Hesse ,  Kai Eichhorn

发明人： Markus Seuring ,  Kay Hesse ,  Kai Eichhorn

IPC分类号： G11C29/00

CPC分类号： G11C29/40 ,  G11C29/44

摘要： In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.

摘要翻译： 在包括大的存储器部分的复杂的半导体器件中，内置的自检电路包括故障捕获逻辑，其允许在给定时刻捕获位图，而不受限于特定的操作条件，与外部接口 测验设备。 因此，虽然由于在自检期间的高速操作可能需要流水线处理，但是可以在保持所考虑的测试算法的高故障覆盖的情况下实现位图的可靠捕获。

公开(公告)号：US20080148120A1

公开(公告)日：2008-06-19

申请号：US11789369

申请日：2007-04-23

申请人： Markus Seuring

发明人： Markus Seuring

IPC分类号： G06F11/25 ,  G06F15/00

CPC分类号： G06F11/2242

摘要： An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture and storing corresponding diagnosis data which include an indication of the failure-causing test data and the corresponding test analysis data. Embodiments are provided which enable that the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test, together with respective diagnosis data.

摘要翻译： 提供了一种集成芯片架构，其允许有效测试集成芯片架构中包括的多个核心并存储相应的诊断数据，其中包括故障测试数据和相应的测试分析数据的指示。 实施例使得测试时间和所需输入/输出测试引脚的数量几乎与包含在多芯片芯片中的核心数量无关。 所提出的实施例提供了多芯片架构，其允许并行地向多个核提供输入数据以同时测试多个核，并且分析所得到的多个测试输出。 作为该分析的结果，实施例可以在芯片上存储尚未成功通过测试的那些核心的指示以及相应的诊断数据。

公开(公告)号：US20070204190A1

公开(公告)日：2007-08-30

申请号：US11484157

申请日：2006-07-11

申请人： Siegfried Hesse ,  Markus Seuring ,  Thomas Herrmann

发明人： Siegfried Hesse ,  Markus Seuring ,  Thomas Herrmann

IPC分类号： G11C29/00

CPC分类号： G11C29/16

摘要： An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational testing. The plurality of test algorithms includes a fault detection test algorithm to perform operational testing of the on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault. The plurality of test algorithms further includes a fault location test algorithm to perform operational testing of the on-chip memory in order to detect and locate a memory fault. Further, a method to perform a memory built-in self test and an MBIST (Memory Built-In Self Test) control circuit template are provided.

摘要翻译： 提供了一种集成电路芯片，其包括片上存储器和测试电路。 测试电路被配置为执行片上存储器的操作测试。 测试电路包括控制器，其被配置为执行从多个测试算法中的选择以执行操作测试。 多个测试算法包括故障检测测试算法，以对片内存储器进行操作测试，以便检测是否存在存储器故障，而不定位存储器故障。 多个测试算法还包括故障定位测试算法，以执行片上存储器的操作测试，以便检测和定位存储器故障。 此外，提供了执行存储器内置自检和MBIST（存储器内置自检）控制电路模板的方法。

公开(公告)号：US09164726B2

公开(公告)日：2015-10-20

申请号：US13697333

申请日：2010-05-10

申请人： Jochen Rivoir ,  Markus Seuring

发明人： Jochen Rivoir ,  Markus Seuring

IPC分类号： G06F7/38 ,  G06F7/00 ,  G01R31/317

CPC分类号： G06F7/00 ,  G01R31/31709 ,  G06F7/38

摘要： An apparatus for determining a number of successive equal bits preceding an edge within a bit stream including a repetitive bit sequence includes an edge number determiner, an edge selector, a time stamper and an equal bits determiner. The edge number determiner determines a preset number of edges. The preset number of edges is coprime to a number of edges of the repetitive bit sequence or coprime to a maximal number of edges of the repetitive bit sequence. The edge selector selects edges of the bit stream spaced apart from each other by the preset number of edges. Further, the time stamper determines a time stamp for each selected edge of the bit stream and the equal bits determiner determines the number of successive equal bits preceding the edge based on determined time stamps of selected edges.

摘要翻译： 一种用于确定包括重复比特序列的比特流之内的边缘之前的连续相等比特数的装置包括边缘号确定器，边缘选择器，时间戳和相等比特确定器。 边缘数确定器确定预设的边数。 预设的边缘数量与重复比特序列的多个边缘或互质的相互重复到重复比特序列的最大边缘数量。 边缘选择器选择彼此间隔开预定数量边缘的比特流的边缘。 此外，时间压模确定位流的每个所选边缘的时间戳，并且相等位确定器基于所选择的边缘的确定的时间戳确定边缘之前的连续相等位数。

公开(公告)号：US20130198252A1

公开(公告)日：2013-08-01

申请号：US13697333

申请日：2010-05-10

申请人： Jochen Rivoir ,  Markus Seuring

发明人： Jochen Rivoir ,  Markus Seuring

IPC分类号： G06F7/00

CPC分类号： G06F7/00 ,  G01R31/31709 ,  G06F7/38

摘要： An apparatus for determining a number of successive equal bits preceding an edge within a bit stream including a repetitive bit sequence includes an edge number determiner, an edge selector, a time stamper and an equal bits determiner. The edge number determiner determines a preset number of edges. The preset number of edges is coprime to a number of edges of the repetitive bit sequence or coprime to a maximal number of edges of the repetitive bit sequence. The edge selector selects edges of the bit stream spaced apart from each other by the preset number of edges. Further, the time stamper determines a time stamp for each selected edge of the bit stream and the equal bits determiner determines the number of successive equal bits preceding the edge based on determined time stamps of selected edges.

摘要翻译： 一种用于确定包括重复比特序列的比特流之内的边缘之前的连续相等比特数的装置包括边缘号确定器，边缘选择器，时间戳和相等比特确定器。 边缘数确定器确定预设的边数。 预设的边缘数量与重复比特序列的多个边缘或互质的相互重复到重复比特序列的最大边缘数量。 边缘选择器选择彼此间隔开预定数量边缘的比特流的边缘。 此外，时间压模确定位流的每个所选边缘的时间戳，并且相等位确定器基于所选择的边缘的确定的时间戳确定边缘之前的连续相等位数。