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    Transistor, memory cell, memory cell array and method of forming a memory cell array
    1.
    发明授权
    Transistor, memory cell, memory cell array and method of forming a memory cell array 失效
    晶体管，存储单元，存储单元阵列和形成存储单元阵列的方法

    公开(公告)号：US07700983B2

    公开(公告)日：2010-04-20

    申请号：US11300853

    申请日：2005-12-15

    申请人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

    发明人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10894 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/785

    摘要： One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove. The lower portion of said gate groove is filled with polysilicon whereas the upper portion of said gate groove is filled with a metal or a metal compound thereby forming a gate electrode disposed along said channel region. Said gate electrode controls an electrical current flowing between said first and second source/drain regions.

    摘要翻译： 本发明的一个实施例涉及至少部分地形成在具有表面的半导体衬底中的晶体管。 特别地，晶体管包括第一源极/漏极区域，第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域。 所述沟道区设置在所述半导体衬底中。 通道方向由连接所述第一和第二源极/漏极区域的线限定。 在所述半导体衬底中形成栅极沟槽。 所述栅极槽与所述沟道区相邻地形成。 所述栅极槽包括上部和下部，所述上部与所述下部相邻，并且栅介质层设置在所述沟道区和所述栅沟之间。 所述栅极沟槽的下部填充有多晶硅，而所述栅极沟槽的上部填充有金属或金属化合物，从而形成沿所述沟道区域设置的栅电极。 所述栅电极控制在所述第一和第二源/漏区之间流动的电流。

    Transistor, memory cell, memory cell array and method of forming a memory cell array
    2.
    发明申请
    Transistor, memory cell, memory cell array and method of forming a memory cell array 失效
    晶体管，存储单元，存储单元阵列和形成存储单元阵列的方法

    公开(公告)号：US20070138523A1

    公开(公告)日：2007-06-21

    申请号：US11300853

    申请日：2005-12-15

    申请人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

    发明人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

    IPC分类号： H01L29/94 ,  H01L21/8244

    CPC分类号： H01L27/10894 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/785

    摘要： One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove. The lower portion of said gate groove is filled with polysilicon whereas the upper portion of said gate groove is filled with a metal or a metal compound thereby forming a gate electrode disposed along said channel region. Said gate electrode controls an electrical current flowing between said first and second source/drain regions.

    摘要翻译： 本发明的一个实施例涉及至少部分地形成在具有表面的半导体衬底中的晶体管。 特别地，晶体管包括第一源极/漏极区域，第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域。 所述沟道区设置在所述半导体衬底中。 通道方向由连接所述第一和第二源极/漏极区域的线限定。 在所述半导体衬底中形成栅极沟槽。 所述栅极槽与所述沟道区相邻地形成。 所述栅极槽包括上部和下部，所述上部与所述下部相邻，并且栅介质层设置在所述沟道区和所述栅沟之间。 所述栅极沟槽的下部填充有多晶硅，而所述栅极沟槽的上部填充有金属或金属化合物，从而形成沿所述沟道区域设置的栅电极。 所述栅电极控制在所述第一和第二源/漏区之间流动的电流。

    Semiconductor Device Comprising Through Hole Vias Having a Stress Relaxation Mechanism
    4.
    发明申请
    Semiconductor Device Comprising Through Hole Vias Having a Stress Relaxation Mechanism 有权
    包含通孔的半导体器件具有应力松弛机制

    公开(公告)号：US20120001330A1

    公开(公告)日：2012-01-05

    申请号：US12970553

    申请日：2010-12-16

    申请人： Torsten Huisinga ,  Michael Grillberger ,  Jens Hahn

    发明人： Torsten Huisinga ,  Michael Grillberger ,  Jens Hahn

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L21/76898 ,  H01L21/7682 ,  H01L23/481 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor device, through hole vias or through silicon vias (TSV) may be formed so as to include an efficient stress relaxation mechanism, for instance provided on the basis of a stress relaxation layer, in order to reduce or compensate for stress forces caused by a pronounced change in volume of the conductive fill materials of the through hole vias. In this manner, the high risk of creating cracks and delamination events in conventional semiconductor devices may be significantly reduced.

    摘要翻译： 在半导体器件中，可以形成通孔过孔或通过硅通孔（TSV），以便包括例如基于应力松弛层提供的有效的应力松弛机构，以便减少或补偿所引起的应力 通过通孔过孔的导电填充材料的体积显着变化。 以这种方式，可以显着降低在常规半导体器件中产生裂纹和分层事件的高风险。

    Process for fabricating an interconnect for contact holes
    5.
    发明授权
    Process for fabricating an interconnect for contact holes 失效

    公开(公告)号：US06602788B2

    公开(公告)日：2003-08-05

    申请号：US09894942

    申请日：2001-06-28

    申请人： Axel Bürke ,  Jens Hahn ,  Sven Schmidbauer

    发明人： Axel Bürke ,  Jens Hahn ,  Sven Schmidbauer

    IPC分类号： H01L2144

    CPC分类号： H01L21/76877 ,  H01L21/2855 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A process for fabricating an interconnect for contact holes includes forming contact holes in an insulation layer leading to a first interconnect layer, cleaning the hole surface, forming a barrier layer on the hole surface, forming an AlGeCu-containing second interconnect layer on the insulation surface by a low-temperature PVD process to fill up the contact holes, forming and patterning a mask layer, and patterning the second interconnect layer by an anisotropic etching process using the mask layer. Due to the relatively small grain sizes and precipitations that are formed in the process, the layer can be patterned directly in a subsequent patterning step, resulting in an extremely reliable and inexpensive interconnect that is easy to integrate in existing process sequences.

    Semiconductor device comprising through hole vias having a stress relaxation mechanism
    6.
    发明授权
    Semiconductor device comprising through hole vias having a stress relaxation mechanism 有权
    半导体装置包括具有应力松弛机构的通孔

    公开(公告)号：US08598714B2

    公开(公告)日：2013-12-03

    申请号：US12970553

    申请日：2010-12-16

    申请人： Torsten Huisinga ,  Michael Grillberger ,  Jens Hahn

    发明人： Torsten Huisinga ,  Michael Grillberger ,  Jens Hahn

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76898 ,  H01L21/7682 ,  H01L23/481 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor device, through hole vias or through silicon vias (TSV) may be formed so as to include an efficient stress relaxation mechanism, for instance provided on the basis of a stress relaxation layer, in order to reduce or compensate for stress forces caused by a pronounced change in volume of the conductive fill materials of the through hole vias. In this manner, the high risk of creating cracks and delamination events in conventional semiconductor devices may be significantly reduced.

    摘要翻译： 在半导体器件中，可以形成通孔过孔或通过硅通孔（TSV），以便包括例如基于应力松弛层提供的有效的应力松弛机构，以便减少或补偿所引起的应力 通过通孔过孔的导电填充材料的体积显着变化。 以这种方式，可以显着降低在常规半导体器件中产生裂纹和分层事件的高风险。

    Fabrication method for an integrated circuit structure
    7.
    发明申请
    Fabrication method for an integrated circuit structure 审中-公开
    集成电路结构的制造方法

    公开(公告)号：US20080124920A1

    公开(公告)日：2008-05-29

    申请号：US11985067

    申请日：2007-11-13

    申请人： Clemens Fitz ,  Axel Buerke ,  Jens Hahn ,  Frank Jakubowski ,  Tobias Mono ,  Joern Regul ,  Sven Schmidbauer

    发明人： Clemens Fitz ,  Axel Buerke ,  Jens Hahn ,  Frank Jakubowski ,  Tobias Mono ,  Joern Regul ,  Sven Schmidbauer

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L29/4941

    摘要： The present invention provides a fabrication method for an integrated circuit structure comprising the steps of forming a electrode layer stack (5, 6′, 7′, 8′) by sequentially depositing a polysilicon layer (5) on a gate dielectric layer (9); a contact layer (6′) composed of Ti on the polysilicon layer (5); a barrier layer (7′) composed of WN on the contact layer (6′); and a metal layer (8′) composed of W on the barrier layer (7′); wherein steps iii) and iv) are carried out as PVD steps using krypton and/or xenon as sputtering gas; and annealing the layer stack (5, 6′, 7′, 8′) in a thermal step in the temperature range of between 600 and 950° C.

    摘要翻译： 本发明提供了一种用于集成电路结构的制造方法，包括以下步骤：通过在栅介电层（9）上依次沉积多晶硅层（5）形成电极层堆叠（5,6'，7'，8' ; 在多晶硅层（5）上由Ti构成的接触层（6'）; 在接触层（6'）上由WN组成的阻挡层（7'）; 和由阻挡层（7'）上的W构成的金属层（8'）。 其中步骤iii）和iv）作为PVD步骤使用氪和/或氙作为溅射气体进行; 并且在600-950℃的温度范围内的热步骤中退火层堆叠（5,6'，7'，8'）。

    Manufacturing method for an integrated semiconductor contact structure having an improved aluminum fill
    8.
    发明申请
    Manufacturing method for an integrated semiconductor contact structure having an improved aluminum fill 审中-公开
    具有改进的铝填充的集成半导体接触结构的制造方法

    公开(公告)号：US20070243708A1

    公开(公告)日：2007-10-18

    申请号：US11402675

    申请日：2006-04-12

    申请人： Jens Hahn ,  Tom Richter ,  Detlef Weber ,  Chung-Hsin Lin

    发明人： Jens Hahn ,  Tom Richter ,  Detlef Weber ,  Chung-Hsin Lin

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： C23C14/046 ,  H01L21/2855 ,  H01L21/76882

    摘要： The present invention provides a manufacturing method for an integrated semiconductor contact structure having an improved Aluminum fill comprising the steps of: forming contact holes in an insulation layer provided on a wafer, said contact holes having a respective bottom and respective sidewalls, said bottoms including a respective conductive area; introducing said wafer into a first PVD deposition chamber, said first PVD deposition chamber including a wafer bias means; and cold depositing a first Aluminum layer on the wafer in said first PVD deposition chamber, said first Aluminum layer covering said bottoms and said sidewalls of said contact holes and forming a seed layer; wherein during said step of cold depositing said first Aluminum layer on the wafer in said first PVD deposition chamber said wafer bias means is set to a bias in the range between 20 W and 700 W or −50 V to −800 V.

    摘要翻译： 本发明提供一种具有改进的铝填充物的集成半导体接触结构的制造方法，包括以下步骤：在设置在晶片上的绝缘层中形成接触孔，所述接触孔具有相应的底部和相应的侧壁，所述底部包括 各导电面积; 将所述晶片引入第一PVD沉积室，所述第一PVD沉积室包括晶片偏置装置; 并且在所述第一PVD沉积室中在所述晶片上冷沉积第一铝层，所述第一铝层覆盖所述底部和所述接触孔的所述侧壁并形成种子层; 其中在所述第一PVD沉积室中将所述第一铝层冷沉积在所述晶片上的步骤期间，所述晶片偏置装置被设置为在20W和700W之间或-50V至-800V的范围内的偏压。

    Methods of forming conductive structures using a dual metal hard mask technique
    9.
    发明授权
    Methods of forming conductive structures using a dual metal hard mask technique 有权
    使用双金属硬掩模技术形成导电结构的方法

    公开(公告)号：US08859418B2

    公开(公告)日：2014-10-14

    申请号：US13348256

    申请日：2012-01-11

    申请人： Torsten Huisinga ,  Jens Hahn ,  Kai Frohberg

    发明人： Torsten Huisinga ,  Jens Hahn ,  Kai Frohberg

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/31144

    摘要： Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench.

    摘要翻译： 本文公开了使用双金属硬掩模积分技术形成导电结构（例如导电线和通孔）的各种方法。 在一个示例中，该方法包括形成第一绝缘材料层，在第一绝缘材料层上方形成第一图案化金属硬掩模层，在第一图案化金属硬掩模层上方形成第二图案化金属硬掩模层， 通过所述第二图案化金属硬掩模层和所述第一图案化金属硬掩模层之间的至少一个蚀刻工艺来限定所述第一绝缘材料层中的沟槽并在所述沟槽中形成导电结构。

    Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique
    10.
    发明申请
    Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique 有权
    使用双金属硬掩模技术形成导电结构的方法

    公开(公告)号：US20130178057A1

    公开(公告)日：2013-07-11

    申请号：US13348256

    申请日：2012-01-11

    申请人： Torsten Huisinga ,  Jens Hahn ,  Kai Frohberg

    发明人： Torsten Huisinga ,  Jens Hahn ,  Kai Frohberg

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76816 ,  H01L21/31144

    摘要： Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench.

    摘要翻译： 本文公开了使用双金属硬掩模积分技术形成导电结构（例如导电线和通孔）的各种方法。 在一个示例中，该方法包括形成第一绝缘材料层，在第一绝缘材料层上方形成第一图案化金属硬掩模层，在第一图案化金属硬掩模层上方形成第二图案化金属硬掩模层， 通过所述第二图案化金属硬掩模层和所述第一图案化金属硬掩模层之间的至少一个蚀刻工艺来限定所述第一绝缘材料层中的沟槽并在所述沟槽中形成导电结构。