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    Hybrid analog/digital equalizer architecture for high-speed receiver
    1.
    发明授权
    Hybrid analog/digital equalizer architecture for high-speed receiver 有权

    公开(公告)号：US11876649B2

    公开(公告)日：2024-01-16

    申请号：US17648440

    申请日：2022-01-20

    Applicant: Marvell Asia Pte Ltd

    Inventor： Luke Wang ,  Benjamin Smith ,  Basel Alnabulsi ,  Stephane Dallaire ,  Simon Forey ,  Karthik Raviprakash ,  Praveen Prabha ,  Benjamin T. Reyes

    IPC: H04L25/03 ,  H04L25/02

    CPC classification number: H04L25/03076 ,  H04L25/0232 ,  H04L2025/03433 ,  H04L2025/03605

    Abstract: Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

    SYSTEMS AND METHODS FOR LINEAR VARIABLE GAIN AMPLIFIER
    2.
    发明申请
    SYSTEMS AND METHODS FOR LINEAR VARIABLE GAIN AMPLIFIER 有权

    公开(公告)号：US20220407484A1

    公开(公告)日：2022-12-22

    申请号：US17895771

    申请日：2022-08-25

    Applicant: Marvell Asia Pte Ltd.

    Inventor： Praveen PRABHA ,  Karthik Raviprakash ,  Luke Wang ,  Stephane Dallaire

    IPC: H03G3/30 ,  H03G1/00 ,  H03G3/00

    Abstract: A variable gain amplifier includes input terminals configured to receive a differential input of the variable gain amplifier, output terminals configured to generate a differential output of the variable gain amplifier, the differential output having a gain applied by the variable gain amplifier to the differential input, and an impedance ladder circuit coupled to the input terminals, the impedance ladder circuit comprising a plurality of semiconductor switches configured to receive respective control signals based on a control voltage. The plurality of semiconductors switches are responsive to the respective control signals to adjust the gain of the variable gain amplifier and configured with a predetermined exponential scale such that the impedance ladder circuit causes a slope of the gain of the variable gain amplifier relative to the control voltage to be generally linear.

    HYBRID ANALOG/DIGITAL EQUALIZER ARCHITECTURE FOR HIGH-SPEED RECEIVER
    4.
    发明申请
    HYBRID ANALOG/DIGITAL EQUALIZER ARCHITECTURE FOR HIGH-SPEED RECEIVER 有权

    公开(公告)号：US20230037860A1

    公开(公告)日：2023-02-09

    申请号：US17648440

    申请日：2022-01-20

    Applicant: Marvell Asia Pte Ltd

    Inventor： Luke Wang ,  Benjamin Smith ,  Basel Alnabulsi ,  Stephane Dallaire ,  Simon Forey ,  Karthik Raviprakash ,  Praveen Prabha ,  Benjamin T. Reyes

    IPC: H04L25/03 ,  H04L25/02

    Abstract: Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

    Method and device for high bandwidth receiver for high baud-rate communications
    5.
    发明授权
    Method and device for high bandwidth receiver for high baud-rate communications 有权

    公开(公告)号：US11750166B2

    公开(公告)日：2023-09-05

    申请号：US17148368

    申请日：2021-01-13

    Applicant: Marvell Asia Pte. Ltd.

    Inventor： Stephane Dallaire ,  Ray Luan Nguyen ,  Geoffrey Hatcher

    IPC: H03H7/38 ,  H04B1/16 ,  H03F3/19

    CPC classification number: H03H7/38 ,  H03F3/19 ,  H04B1/16

    Abstract: An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.

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