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公开(公告)号：US20230036435A1
公开(公告)日：2023-02-02
申请号：US17813753
申请日：2022-07-20
Applicant: Marvell Asia Pte Ltd
Inventor： Ray Luan Nguyen , Benjamin Tomas Reyes , Geoffrey Hatcher , Stephen Jantzi
Abstract: Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal. The transceiver circuitry further includes distortion correction circuitry at the one of the analog front end and the digital front end, to determine and apply a distortion cancellation function to the distorted signal.
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公开(公告)号：US20240162928A1
公开(公告)日：2024-05-16
申请号：US18403900
申请日：2024-01-04
Applicant: Marvell Asia Pte Ltd
Inventor： Ray Luan Nguyen , Benjamin Tomas Reyes , Geoffrey Hatcher , Stephen Jantzi
Abstract: Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal. The transceiver circuitry further includes distortion correction circuitry at the one of the analog front end and the digital front end, to determine and apply a distortion cancellation function to the distorted signal.
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公开(公告)号：US20240243751A1
公开(公告)日：2024-07-18
申请号：US18414525
申请日：2024-01-17
Applicant: MARVELL ASIA PTE LTD
Inventor： Benjamin Tomas Reyes , Gabriele Minoia , Ray Luan Nguyen
IPC: H03M1/10
CPC classification number: H03M1/1071 , H03M1/1014
Abstract: An Integrated Circuit (IC) includes one or more functional circuits of a given type, a test circuit including a selected one of the functional circuits or a replica circuit of the same type as the functional circuits, and an Adaptive Voltage Scaling (AVS) circuit. The AVS circuit is configured to determine a delay of the test circuit, and to adjust a supply voltage of the functional circuits in response to the determined delay of the test circuit.
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公开(公告)号：US20230035036A1
公开(公告)日：2023-02-02
申请号：US17813828
申请日：2022-07-20
Applicant: Marvell Asia Pte Ltd
Inventor： Ray Luan Nguyen , Dawood Alam , Nong Fan , Geoffrey Hatcher , Morteza Azarmnia
Abstract: A high-speed data receiver includes interleaver circuitry configured to divide a received data stream into a plurality of interleaved paths for processing, spectral content detection circuitry configured to derive spectral content information from data on each of the plurality of interleaved paths, sorting circuitry configured to bin the derived spectral content information according to energy levels, stream attribute determination circuitry configured to determine, based on sorted spectral content, one or more of path offsets of the interleaved paths, gain mismatch among interleaved paths, signal bandwidth mismatch and pulse width mismatch, and equalization circuitry configured to correct the one or more of the determined offsets, the determined gain mismatch and the determined signal width mismatch. Equalization circuitry may be configured to equalize a gain-normalized signal by separately adjusting respective bandwidth actuators of each respective interleaved path and respective pulse width actuators of each respective interleaved path.
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公开(公告)号：US12294399B2
公开(公告)日：2025-05-06
申请号：US18403900
申请日：2024-01-04
Applicant: Marvell Asia Pte Ltd
Inventor： Ray Luan Nguyen , Benjamin Tomas Reyes , Geoffrey Hatcher , Stephen Jantzi
Abstract: Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal. The transceiver circuitry further includes distortion correction circuitry at the one of the analog front end and the digital front end, to determine and apply a distortion cancellation function to the distorted signal.
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Patent Agency Ranking
公开(公告)号：US11750166B2
公开(公告)日：2023-09-05
申请号：US17148368
申请日：2021-01-13
Applicant: Marvell Asia Pte. Ltd.
Inventor： Stephane Dallaire , Ray Luan Nguyen , Geoffrey Hatcher
Abstract: An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.
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公开(公告)号：US12009921B2
公开(公告)日：2024-06-11
申请号：US17813828
申请日：2022-07-20
Applicant: Marvell Asia Pte Ltd
Inventor： Ray Luan Nguyen , Dawood Alam , Nong Fan , Geoffrey Hatcher , Morteza Azarmnia
CPC classification number: H04L1/0071 , H04B1/08 , H04B1/1607
Abstract: A high-speed data receiver includes interleaver circuitry configured to divide a received data stream into a plurality of interleaved paths for processing, spectral content detection circuitry configured to derive spectral content information from data on each of the plurality of interleaved paths, sorting circuitry configured to bin the derived spectral content information according to energy levels, stream attribute determination circuitry configured to determine, based on sorted spectral content, one or more of path offsets of the interleaved paths, gain mismatch among interleaved paths, signal bandwidth mismatch and pulse width mismatch, and equalization circuitry configured to correct the one or more of the determined offsets, the determined gain mismatch and the determined signal width mismatch. Equalization circuitry may be configured to equalize a gain-normalized signal by separately adjusting respective bandwidth actuators of each respective interleaved path and respective pulse width actuators of each respective interleaved path.
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公开(公告)号：US11901925B2
公开(公告)日：2024-02-13
申请号：US17813753
申请日：2022-07-20
Applicant: Marvell Asia Pte Ltd
Inventor： Ray Luan Nguyen , Benjamin Tomas Reyes , Geoffrey Hatcher , Stephen Jantzi
Abstract: Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal. The transceiver circuitry further includes distortion correction circuitry at the one of the analog front end and the digital front end, to determine and apply a distortion cancellation function to the distorted signal.
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公开(公告)号：US11750207B2
公开(公告)日：2023-09-05
申请号：US17722749
申请日：2022-04-18
Applicant: Marvell Asia Pte Ltd.
Inventor： Ray Luan Nguyen , Geoffrey Hatcher
CPC classification number: H03M1/1215 , H03M1/0626 , H03M1/1255 , H03M1/282 , H03M1/362
Abstract: A multi-instance time-interleaving (TI) system and method of operation therefor. The system includes a plurality of TI devices, each with a plurality of clock generation units (CGUs) coupled to an interleaver network. Within each TI device, the plurality of CGUs provides a plurality of clock signals needed by the interleaver network. A phase detector device is coupled to the plurality of TI devices and configured to determine any phase differences between the clock signals of a designated reference TI device and the corresponding clock signals of each other TI device. To determine the phase differences, the phase detector can use a logic comparator configuration, a time-to-digital converter (TDC) configuration, or an auto-correlation configuration. The phases of the clock signals of each other TI device can be aligned to the reference TI device using internal phase control, retimers, delay cells, finite state machines, or the like.
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10.发明授权公开(公告)号：US11507129B2
公开(公告)日：2022-11-22
申请号：US17504850
申请日：2021-10-19
Applicant: MARVELL ASIA PTE, LTD.
Inventor： Ray Luan Nguyen , Geoffrey O. Hatcher
Abstract: A multi-layer time-interleaving (TI) device and method of operation therefor. This device includes a plurality of TI layers configured to receive a plurality of input clock signals and to output a plurality of output clock signals, each of which can be configured to drive subsequent devices. The layers include at least a first and second layer including a fine-grain propagation device and a barrel-shifting propagation device configured to retime the plurality of input clock signals to produce divided output clock signals. The device can include additional barrel-shifting propagation devices to time interleave an initial two layers to produce one or more additional layers. Using negative phase stepping, the plurality of output clock signals is produced with optimal timing margin and synchronized on a single clock edge.
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